XR16L788IQ-F Exar Corporation, XR16L788IQ-F Datasheet - Page 13

• Manufacturer Part Number: XR16L788IQ-F
• Description: IC UART 64B 3.3V OCTAL 100QFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR16L788IQ-F

• Number Of Channels: 8
• Package / Case: 100-BQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1284

REV. 1.2.3
The THR and RHR register addresses for channel 0 to channel 7 is shown in
RHR for channels 0 to 7 are located at address 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60 and 0x70
respectively. Transmit data byte is loaded to the THR when writing to that address and receive data is
unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550
compatible in 8-bit format, so each bus operation can only write or read in bytes.
.
Automatic RTS/DTR flow control is used to prevent data overrun to the local receiver FIFO. The RTS#/DTR#
output pin is used to request remote unit to suspend/resume data transmission. The flow control features are
individually selected to fit specific application requirement (see
•
•
•
•
With the Auto RTS function enabled, the RTS# output pin will not be de-asserted (HIGH) when the receive
FIFO reaches the programmed trigger level, but will be de-asserted when the FIFO reaches the next trigger
level for Trigger Tables A-C
is unloaded to the next trigger level below the programmed trigger level.
2.9
2.10
Select RTS (and CTS) or DTR (and DSR) through MCR bit-2.
Enable auto RTS/DTR flow control using EFR bit-6.
The auto RTS or auto DTR function must be started by asserting the RTS# or DTR# output pin (MCR bit-1 or
bit-0 to a logic 1, respectively) after it is enabled.
If using programmable RX FIFO trigger levels, hysteresis levels can be selected via FCTR bits 3-0.
THR and RHR Register Locations
Automatic RTS/DTR Hardware Flow Control Operation
T
ABLE
CH0 0x00 Read RHR
CH2 0x20 Read RHR
CH3 0x30 Write THR
CH3 0x30 Read RHR
CH4 0x40 Read RHR
CH0 0x00 Write THR
CH1 0x10 Write THR
CH1 0x10 Read RHR
CH2 0x20 Write THR
CH4 0x40 Write THR
CH5 0x50 Write THR
5: T
CH5 0x50 Read RHR
CH7 0x70 Read RHR
CH6 0x60 Read RHR
CH6 0x60 Write THR
CH7 0x70 Write THR
RANSMIT AND
THR and RHR Address Locations For CH0 to CH7 (16C550 Compatible)
(See Table
R
ECEIVE
14). The RTS# output pin will be asserted (LOW) again after the FIFO
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
H
OLDING
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
13
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
R
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
EGISTER
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Figure
L
OCATIONS
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
10):
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
, 16C550
Table 5
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
COMPATIBLE
THRRHR1
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
below. The THR and
XR16L788