XR16L788IQ-F Exar Corporation, XR16L788IQ-F Datasheet - Page 39
![IC UART 64B 3.3V OCTAL 100QFP](/photos/29/6/290689/tqfp100_sml.jpg)
XR16L788IQ-F
Manufacturer Part Number
XR16L788IQ-F
Description
IC UART 64B 3.3V OCTAL 100QFP
Manufacturer
Exar Corporation
Type
IrDA or RS- 485r
Datasheet
1.XR16L788CQ-F.pdf
(54 pages)
Specifications of XR16L788IQ-F
Number Of Channels
8
Package / Case
100-BQFP
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
2.97 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
6.25 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.97 V
Supply Current
5 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V or 5 V
No. Of Channels
8
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1284
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16L788IQ-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR16L788IQ-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
REV. 1.2.3
FCTR[4]: Infrared RX Input Logic Select
•
•
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
•
•
Logic 0 = Select RX input as active high encoded IrDA data, normal, (default).
Logic 1 = Select RX input as active low encoded IrDA data, inverted.
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
Logic 1 = Enable Auto RS485 half duplex direction control. RTS# output changes its logic level from HIGH to
LOW when finished sending the last stop bit of the last character out of the TSR register. It changes from
LOW to HIGH when a data byte is loaded into the THR or transmit FIFO. The change to HIGH occurs prior
sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register
(TSR) empty.
FCTR B
T
ABLE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IT
-3
17: 16 S
FCTR B
ELECTABLE
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
IT
-2
H
YSTERESIS
FCTR B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
L
IT
EVELS
39
-1
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
W
HEN
FCTR B
T
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RIGGER
IT
-0
T
ABLE
RTS/DTR H
-D
(
IS
CHARACTERS
S
+/- 16
+/- 24
+/- 32
+/- 12
+/- 20
+/- 28
+/- 36
+/- 40
+/- 44
+/- 48
+/- 52
+/- 4
+/- 6
+/- 8
+/- 8
ELECTED
0
YSTERESIS
XR16L788
)