XR16L788IQ-F Exar Corporation, XR16L788IQ-F Datasheet - Page 50
![IC UART 64B 3.3V OCTAL 100QFP](/photos/29/6/290689/tqfp100_sml.jpg)
XR16L788IQ-F
Manufacturer Part Number
XR16L788IQ-F
Description
IC UART 64B 3.3V OCTAL 100QFP
Manufacturer
Exar Corporation
Type
IrDA or RS- 485r
Datasheet
1.XR16L788CQ-F.pdf
(54 pages)
Specifications of XR16L788IQ-F
Number Of Channels
8
Package / Case
100-BQFP
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
2.97 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
6.25 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.97 V
Supply Current
5 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V or 5 V
No. Of Channels
8
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1284
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16L788IQ-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR16L788IQ-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR16L788
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
F
F
F
IGURE
IGURE
IGURE
RX
INT#
IN T # *
IO W #
IOR#
(Reading data out
of RX FIFO)
T X
(U n lo a d in g )
(L o a d in g d a ta
in to T H R )
*T X in te rru p t is c le a re d w h e n th e IS R is re a d o r w h e n d a ta is lo a d e d in to th e T H R .
(Unloading)
(Loading data
*TX interrupt is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
22. T
23. R
24. T
into FIFO )
TX
INT#*
IO W #
IE R [1 ]
e n a b le d
RANSMIT
RANSMIT
ECEIVE
TX FIFO
T
Em pty
W R I
enabled
IER [1]
Start
Bit
S
D0:D7
I
NTERRUPT
I
S ta rt
I
NTERRUPT
Trigger Level or RX Data
NTERRUPT
B it
RX FIFO fills up to RX
S
IS R is re a d
Start
Tim eout
B it
ISR is read
D 0 :D 7
S
D0:D7
D 0:D 7
T
T
T
IMING
TX FIFO fills up
IMING
IMING
to trigger level
T
T
S top
Bit
W R I
T
S to p
[FIFO M
B it
[N
[FIFO M
D0:D7
ON
T
S
SSI
-FIFO M
D 0:D 7
ODE
ODE
S
IS R is re a d
]
T
D0:D7
D 0 :D 7
]
S
50
ODE
D 0:D 7
T
W R I
]
T
below trigger level
T
S
TX FIFO drops
T
D0:D7
SI
T
S
D0:D 7
T
S
T
T
W R I
RRI
D0:D7
T
S
ISR is read
D 0:D 7
T
RX FIFO drops
Trigger Level
below RX
S
T
D0:D7
IS R is re a d
D 0 :D 7
T
T
RR
S
Last Data B yte
Transm itted
D 0:D 7
T
REV. 1.2.3