XR16L788IQ-F Exar Corporation, XR16L788IQ-F Datasheet - Page 29

• Manufacturer Part Number: XR16L788IQ-F
• Description: IC UART 64B 3.3V OCTAL 100QFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR16L788IQ-F

• Number Of Channels: 8
• Package / Case: 100-BQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 8
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1284

REV. 1.2.3
N
patibility during Internal loopback, see
SEE”RECEIVER” ON PAGE 11.
SEE”TRANSMITTER” ON PAGE 10.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) register and
also encoded in INT (INT0-INT3) register in the Device Configuration Registers.
When the receive FIFO (FCR BIT-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the
RHR interrupts (see ISR bits 3 and 4) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L788 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
T
4.3.1
4.3.2
A
OTE
1 0 1 1
1 0 1 1
1 1 0 0
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
ABLE
A3-A0
DDRESS
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
2: MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR16L788. They are present for 16C550 com-
12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
Receive Holding Register (RHR) - Read Only
Transmit Holding Register (THR) - Write Only
Interrupt Enable Register (IER) - Read/Write
RXTRG
XCHAR
IER versus Receive FIFO Interrupt Mode Operation
IER versus Receive/Transmit FIFO Polled Mode Operation
RXCNT
XOFF1
XOFF2
XON1
XON2
N
R
AME
EG
W
R
EAD
W
W
W
W
W
RITE
R
R
/
B
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
IT
0
-7
Figure 12
B
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
IT
0
-6
.
B
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
IT
0
-5
29
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART
B
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
IT
0
-4
B
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
IT
0
-3
B
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
IT
0
-2
S
HADED BITS ARE ENABLED BY
Xon Det.
Indicator
B
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
IT
-1
Xoff Det.
Indicator
B
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
IT
XR16L788
-0
C
after read
Self-clear
EFR B
OMMENT
IT
-4.