AT86RF211SAH-R Atmel, AT86RF211SAH-R Datasheet - Page 34

• Manufacturer Part Number: AT86RF211SAH-R
• Description: IC RF TXRX FSK 400-950MHZ 48TQFP
• Manufacturer: Atmel

Specifications of AT86RF211SAH-R

• Frequency: 400MHz ~ 950MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 7dBm ~ 12dBm
• Sensitivity: -107dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Current - Transmitting: -
• Current - Receiving: -

2.5
2.5.1
2.5.1.1
34
Control Logic
AT86RF211S
Serial Data Interface
Register Interface Format
Table 2-13.
More information is given in the Application Note “Power Management Using the
Embedded Stand-alone Wake-up Mode Protocol. Rev. 2” reference 2186.
The application microcontroller can control and monitor the AT86RF211S through a syn-
chronous, bi-directional 3-wire serial interface, comprising three signals:
When SLE = 1, the interface is inhibited and the SCK and SDATA (in) values are not
propagated into the IC, reducing power consumption and preventing any risk of parasitic
write or read cycle.
A read or write cycle starts when SLE is set to 0 and stops when SLE is set to 1. Only
one operation can be performed during one access cycle, meaning that only one regis-
ter can be either read or written.
A message comprises three fields:
A variable register length and partial read or write cycles are supported.
In the case of partial read or write cycles, the first data (in or out) is always the register’s
MSB.
• SLE signal: enable input
• SCK signal: clock input
• SDATA signal: data in/out
• Address A[3:0]: 4 bits (MSB first)
• R/W: read/write selection
• Data D[31:0]: up to 32 bits (MSB first)
A[3]
WL2[2:0]
(000)
(001)
(010)
(011)
(100)
(101)
(110)
(111)
A[2]
ADDRESS
2
2
2
2
2
2
2
2
WL2 Programming
A[1]
A[0]
16 × WL1
31 × WL1
1 × WL1
2 × WL1
3 × WL1
4 × WL1
8 × WL1
Period
0
R/W
R/W
MSB
Simultaneous test of the RSSI and header
DATA up to 32 bits (Variable Length)
Comments
D[nbit-1:0]
5348B–WIRE–03/06
LSB