AT86RF211SAH-R Atmel, AT86RF211SAH-R Datasheet - Page 38

• Manufacturer Part Number: AT86RF211SAH-R
• Description: IC RF TXRX FSK 400-950MHZ 48TQFP
• Manufacturer: Atmel

Specifications of AT86RF211SAH-R

• Frequency: 400MHz ~ 950MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 7dBm ~ 12dBm
• Sensitivity: -107dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Current - Transmitting: -
• Current - Receiving: -

Table 2-14.
Note:
2.5.2.1
2.5.2.2
2.5.2.3
Table 2-15.
38
Name
-
-
CTRL2
Name
nbit
init
All the registers must be reprogrammed after the voltage supply has been removed, otherwise they will remain in the default
state
AT86RF211S
PDN
31
Reset Register (RESET)
Control Register (CTRL1)
0
Register Overview
CTRL1 Overview
Address A[3:0]
RXTX
30
0
(1101)
(1110)
(1111)
2
2
2
DATACLK
Writing in this register (0 or 1) triggers an asynchronous reset. This register can only be
written.
All registers return to the reset state. The chip returns to power-down mode. All the fol-
lowing blocks are reset:
And in the power-down state, reset is applied to the following blocks:
From powering up the supplies, it takes about 10 µs or at least 1.8V before the reset
state is established (power-on reset). From resetting the device, one should wait about
10 µs before re-programming.
Please note that for compatibility reasons, any reset triggered by a power-on sequence
or an access to the RESET register sets the device to RF211 mode.
29
0
• Registers revert to their default value, therefore the device is compatible with the
• Wake-up function
• Clock recovery function
• Synthesizer dividers
• Clock recovery function
• PLL lock detect
• RSSI detection block
• Discriminator clock (455 kHz)
AT86RF211
Nbits
TXLOCK
32
28
1
Name
Reset
PAPDN
Read-Write
27
0
R-W
WUEN
26
0
Comments
Reserved
Reserved
Control register (lock detect - clock recovery)
LNAGSEL
25
0
MVCC
24
0
Bit Number
0
(000000)
TRSSI
23-18
5348B–WIRE–03/06
2
HRSSI
(000)
17-15
2