AT86RF211SAH-R Atmel, AT86RF211SAH-R Datasheet - Page 36

IC RF TXRX FSK 400-950MHZ 48TQFP

AT86RF211SAH-R

Manufacturer Part Number
AT86RF211SAH-R
Description
IC RF TXRX FSK 400-950MHZ 48TQFP
Manufacturer
Atmel
Datasheet

Specifications of AT86RF211SAH-R

Frequency
400MHz ~ 950MHz
Data Rate - Maximum
100kbps
Modulation Or Protocol
FSK
Applications
ISM
Power - Output
7dBm ~ 12dBm
Sensitivity
-107dBm
Voltage - Supply
2.4 V ~ 3.6 V
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Memory Size
-
Current - Transmitting
-
Current - Receiving
-
2.5.1.3
Figure 2-30. Read Chronogram: Complete Read Cycle from a 10-bit Register
36
AT86RF211S
SLE
SCK
SDATA
SDATA
Direction
READ Mode (R/W = 0)
A[3]
A[2 ]
INPUT
The address and R/W bits are clocked on the rising edge of SCK and the data bits are
changed on the falling edge of SCK. The register’s MSB is the first bit read.
The SDATA I/O pin is switched from input to output on the edge following the 1 clocking
the R/W bit.
It is possible to stop reading a register (by reverting SLE to 1) at any time.
If an attempt is detected to read more bits than the register capacity, SDATA is clamped
to 0.
If the address of a register is not valid, SDATA is set to 1 during the first 32 SCK periods,
and then to 0 during all the extra periods.
SDATA is switched back to the input state when SLE reverts to 1.
Figure 2-31. Read Chronogram: Partial Read Cycle, Reading 2 Bits
A[1]
A[0]
R/W
SLE
SCK
SDATA
SDATA
Mode
D[9 ]
D[8]
D[7]
A[3]
D[6]
A[2]
INPUT
D[5]
OUTPUT
A[1]
D[4]
A[0]
D[3]
R/W
D[2]
D[31]
OUTPUT
D[1]
D[30]
D[0]
INPUT
INPUT
5348B–WIRE–03/06

Related parts for AT86RF211SAH-R