XRT94L31IB-L Exar Corporation, XRT94L31IB-L Datasheet - Page 112

• Manufacturer Part Number: XRT94L31IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
Table 13
Ingress Direction) for STS-1/STM-0 Applications and when the Receive STS-1 TOH Processor block has been
configured to sample the DS3/E3/STS_1_DATA_IN signal upon the rising edge of DS3/E3/
STS_1_CLOCK_IN.
Table 14
Ingress Direction) for STS-1/STM-0 Applications and when the Receive STS-1 TOH Processor block has been
configured to sample the DS3/E3/STS_1_DATA_IN signal upon the falling edge of DS3/E3/
STS_1_CLOCK_IN.
The user should be aware of the followings things about the Egress DS3/E3/STS-1 Interface timing.
a. If a given channel is configured to operate in the DS3/E3 Mode, then the DS3/E3 Framer block can be
b. If a given channel is configured to operate in the STS-1/STM-0 Mode, then the Transmit STS-1 TOH
c. Further, if a given channel is configured to operate in the STS-1/STM-0 Mode, then the Transmit STS-1
The Timing Diagram for the Egress DS3/E3/STS-1 Interface is presented below in
1.3.5
1.3.6
S
S
YMBOL
YMBOL
t10
t10
t9
t9
configured to output the outbound DS3/E3 data (via the DS3/E3/STS_1_DATA_OUT and DS3/E3/
STS_1_NEG_OUT output pins) upon either the rising or falling edge of DS3/E3/STS_1_CLOCK_OUT.
Processor block will be operating in the Single-Rail Mode (e.g., the Transmit STS-1 TOH Processor block
will output all outbound STS-1/STM-0 data via the DS3/E3/STS_1_DATA_OUT output pin. No data will be
output via the DS3/E3/STS_1_NEG_OUT output pin).
TOH Processor block can be configured to output the outbound STS-1/STM-0 data (via the DS3/E3/
STS_1_DATA_OUT pin) either upon the rising or falling edge of DS3/E3/STS_1_CLOCK_OUT.
T
T
ABLE
ABLE
presents information on the Timing parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
presents information on the Timing parameters for the DS3/E3/STS-1 LIU Interface Signals (in the
Ingress Timing for STS-1/STM-0 Applications
DS3/E3/STS_1_DATA_IN to rising edge of DS3/E3/STS_1_CLOCK_IN
set-up time requirements
Rising edge of DS3/E3/STS_1_CLK_IN to DS3/E3/STS_1_DATA_IN and
DS3/E3/STS_1_CLOCK_IN Hold time requirements
DS3/E3/STS_1_DATA_IN to falling edge of DS3/E3/STS_1_CLOCK_IN
set-up time requirements
Falling edge of DS3/E3/STS_1_CLK_IN to DS3/E3/STS_1_DATA_IN and
DS3/E3/STS_1_CLOCK_IN Hold time requirements
The Egress DS3/E3/STS-1 Interface Timing
13: T
14: T
IMING
IMING
I
I
NFORMATION FOR THE
NFORMATION FOR THE
A
A
PPLICATIONS
PPLICATIONS
(
D
D
FALLING EDGE OF
(
RISING EDGE OF
ESCRIPTION
ESCRIPTION
I
I
NGRESS
NGRESS
112
DS3/E3/STS-1 LIU I
DS3/E3/STS-1 LIU I
DS3/E3/STS_1_CLOCK_IN)
DS3/E3/STS_1_CLOCK_IN)
NTERFACE FOR
NTERFACE FOR
M
M
4ns
0ns
4ns
0ns
Figure
IN
IN
.
.
17.
STS-1/STM-0
STS-1/STM-0
T
T
YP
YP
.
.
REV. 1.0.1
M
M
AX
AX
.
.