XRT94L31IB-L Exar Corporation, XRT94L31IB-L Datasheet - Page 22

• Manufacturer Part Number: XRT94L31IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L31IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
D6
B4
SIGNAL NAME
TxLDCCEnable
TxTOHIns
I/O
O
I
TTL
CMOS
TYPE
Transmit TOH Input Port - Insert Enable Input pin:
This input pin, along with the TxTOH input pin, and the TxTOHEnable,
TxTOHFrame and TxTOHClk output pins function as the Transmit TOH
Input Port.
This input pin is used to either enable or disable the Transmit TOH Input
Port.
abled and will not sample and insert (into the outbound STS-3 data
stream) any data residing on the TxTOH input, upon the rising edge of
TxTOHClk.
If this input pin is "High", then the Transmit TOH Input Port will be
enabled. In this mode, whenever the TxTOHEnable output pin is also
"High", the Transmit TOH Input Port will sample and latch any data that
is presented on the TxTOH input pin, upon the rising edge of TxTOHClk.
To externally insert user values of TOH into the outbound STS-3 data
stream via the Transmit TOH Input Port, do the following.
•
•
•
N
Transmit - Line DCC Input Port - Enable Output pin:
This output pin, along with the TxTOHClk output pin and the TxLDCC
input pin are used to insert their value for the D4, D5, D6, D7, D8, D9,
D10, D11 and D12 bytes into the Transmit STS-3 TOH Processor Block.
The Transmit STS-3 TOH Processor block will accept this data and will
insert into the D4, D5, D6, D7, D8, D9, D10, D11 and D12 byte-fields,
within the outbound STS-3 data-stream.
The Line DCC HDLC Controller circuitry (which is connected to the
TxTOHClk, the TxSDCC and this output pin, is suppose to do the follow-
ing.
It should continuously monitor the state of this output pin.
Whenever this output pin pulses "High", then the Line DCC HDLC Con-
troller circuitry should place the next Line DCC bit (to be inserted into the
Transmit STS-3 TOH Processor block) onto the TxLDCC input pin, upon
the rising edge of TxTOHClk.
Any data that is placed on the TxLDCC input pin, will be sampled upon
the falling edge of TxOHClk.
If this input pin is "Low", then the Transmit TOH Input Port will be dis-
OTES
Continuously sample the state of TxTOHFrame and TxTOHEnable
upon the rising edge of TxTOHClk.
Whenever the TxTOHEnable output pin is sampled "High" then the
user's external circuitry should drive this input pin "High".
Next, output the next TOH bit, onto the TxTOH input pin, upon the
falling edge of TxTOHClk. The Transmit TOH Input Port will sample
the data (on this input pin) upon the falling edge of TxTOHClk.]
1. Data applied to the TxTOH input pin will be sampled according
2. For DCC, E1, F1, E2 bytes, TxTOH input pin will be sampled if
3. For other TOH bytes, TxTOH input pin will be sampled if both
:
to the following insertion priority scheme:
both TxTOHEnable and TxTOHIns are "High".
TxTOHEnable and TxTOHIns are "High" or if both TxTOHIns
and Software Insertion Enabled are "Low".
22
DESCRIPTION
REV. 1.0.1