EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 177

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.3.2.2 Clock Generation
2010-12-21 - d0034_Rev0.90
Table 15.5. USART Parity Bits
The USART clock defines the transmission and reception data rate. When operating in asynchronous
mode, the baud rate (bit-rate) is given by Equation 15.1 (p. 177)
USART Baud Rate
where f
oversampling rate as defined by OVS in USARTn_CTRL, see Table 15.6 (p. 177) .
Table 15.6. USART Oversampling
The USART has a fractional clock divider to allow the USART clock to be controlled more accurately
than what is possible with a standard integral divider.
The clock divider used in the USART is a 15-bit value, with a 13-bit integral part and a 2-bit fractional
part. The fractional part is configured in the two LSBs of DIV in USART_CLKDIV. The lowest achievable
baud rate at 32 MHz is about 244 bauds/sec.
Fractional clock division is implemented by distributing the selected fraction over four baud periods. The
fractional part of the divider tells how many of these periods should be extended by one peripheral clock
cycle.
Given a desired baud rate brdesired, the clock divider USARTn_CLKDIV can be calculated by using
Equation 15.2 (p. 177) :
USART Desired Baud Rate
Table 15.7 (p. 178) shows a set of desired baud rates and how accurately the USART is able to
generate these baud rates when running at a 4 MHz peripheral clock, using 16x or 8x oversampling.
STOP BITS [1:0]
00
01
10
11
OVS [1:0]
00
01
10
11
HFPERCLK
USARTn_CLKDIV = 256 x (f
br = f
is the peripheral clock (HFPERCLK
HFPERCLK
/(oversample x (1 + USARTn_CLKDIV/256))
HFPERCLK
...the world's most energy friendly microcontrollers
177
/(oversample x brdesired) - 1)
Description
No parity bit (Default)
Reserved
Even parity
Odd parity
oversample
16
8
6
4
USARTn
) frequency and oversample is the
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(15.1)
(15.2)