EFM32TG210F32 Energy Micro, EFM32TG210F32 Datasheet - Page 20

• Manufacturer Part Number: EFM32TG210F32
• Description: MCU 32BIT 32KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Tiny Geckor

Specifications of EFM32TG210F32

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Processor To Be Evaluated: EFM32TG210
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.3.1.2 Reading
5.3.2 FREEZE register
5.4 Flash
2010-12-21 - d0034_Rev0.90
When reading from a Low Energy Peripheral, the data read is synchronized regardless if it originates
in the Low Energy clock domain or core clock domain. Registers which are updated/ maintained by the
Low Energy Peripheral are read directly from the Low Energy clock domain. Registers which originate in
the core clock domain, are read from the core clock domain. See Figure 5.3 (p. 20) for an overview
of the reading operation.
Note
Figure 5.3. Read operation form Low Energy Peripherals
In Low Energy Peripheral with delayed synchronization there is a <module_name>_FREEZE register
(e.g. RTC_FREEZE). The register contains a bit named REGFREEZE. If precise control of the
synchronization process is required, this bit may be utilized. When REGFREEZE is set, the
synchronization process is halted allowing the software to write multiple Low Energy registers before
starting the synchronization process, thus providing precise control of the module update process. The
synchronization process is started by clearing the REGFREEZE bit.
Note
The Flash retains data in any state and typically stores the application code, special user data and
security information. The Flash memory is typically programmed through the debug interface, but can
also be erased and written to from software.
Core Clock Dom ain
Synchronizer
Core Clock
Read Data
If compatibility with the Gecko series is a requirement for a given application, the rules that
apply to delayed synchronization with respect to SYNCBUSY should also be followed for
the peripherals that support immediate synchronization.
Writing a register and then immediately reading the new value of the register may give the
impression that the write operation is complete. This may not be the case. Please refer
to the SYNCBUSY register for correct status of the write operation to the Low Energy
Peripheral.
The FREEZE register is also present on peripherals with immediate synchronization, but
there it has no effect
Read
Register 0
Register 1
Register n
.
.
.
Freeze
...the world's most energy friendly microcontrollers
HW Status Register m
20
Low Frequency Clock
HW Status Register 0
HW Status Register 1
Synchronizer 0
Synchronizer 1
Low Frequency Clock Dom ain
Synchronizer n
.
.
.
.
.
.
Low Frequency Clock
www.energymicro.com
Register 0 Sync
Register 1 Sync
Register n Sync
Low Energy
Peripheral
Function
Main
.
.
.