AT25DF081A-MH-T Atmel, AT25DF081A-MH-T Datasheet - Page 15

• Manufacturer Part Number: AT25DF081A-MH-T
• Description: IC FLASH 8MBIT SPI 8UDFN
• Manufacturer: Atmel

Specifications of AT25DF081A-MH-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 8M (4096 pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-UDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Atmel AT25DF081A
8.3
Block Erase
A block of 4-, 32-, or 64-Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one
of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode
of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase. Before a Block Erase
command can be started, the Write Enable command must have been previously issued to the device to set the
WEL bit of the Status Register to a logical “1” state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must
be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address
within the 4-, 32-, or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device
will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the
block is internally self-timed and should take place in a time of t
.
BLKE
Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded
by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values
can be either a logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored, and for a 64-Kbyte
erase, address bits A15-A0 will be ignored by the device. Despite the lower order address bits not being decoded
by the device, the complete three address bytes must still be clocked into the device before the CS pin is deas-
serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the
device will abort the operation and no erase operation will be performed.
If the address specified by A23-A0 points to a memory location within a sector that is in the protected or locked
down state, then the Block Erase command will not be executed, and the device will return to the idle state once
the CS pin has been deasserted.
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an
incomplete address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory
location within the region to be erased is protected or locked down.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the
t
time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL
BLKE
bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase prop-
erly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.
Figure 8-5.
Block Erase
CS
0
1
2
3
4
5
6
7
8
9
10 11
12
26
27 28
29 30
31
SCK
OPCODE
ADDRESS BITS A23-A0
SI
C
C
C
C
C
C
C
C
A
A
A
A
A
A
A
A
A
A
A
A
MSB
MSB
HIGH-IMPEDANCE
SO
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