AT25DF081A-MH-T Atmel, AT25DF081A-MH-T Datasheet - Page 8

• Manufacturer Part Number: AT25DF081A-MH-T
• Description: IC FLASH 8MBIT SPI 8UDFN
• Manufacturer: Atmel

Specifications of AT25DF081A-MH-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 8M (4096 pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-UDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.
7.1
Figure 7-1.
8
SCK
SO
CS
SI
Read Commands
Read Array
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply
providing the clock signal once the initial starting address has been specified. The device incorporates an internal
address counter that automatically increments on every clock cycle.
Three opcodes (1Bh, 0Bh, and 03h) can be used for the Read Array command. The use of each opcode depends
on the maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at
any clock frequency up to the maximum specified by f
read operations up to the maximum specified by f
sible and can be used at any clock frequency up to the maximum specified by f
opcode at clock frequencies above f
To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (1Bh, 0Bh, or
03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be
clocked in to specify the starting address location of the first byte to read within the memory array. Following the
three address bytes, additional dummy bytes may need to be clocked into the device depending on which opcode
is used for the Read Array operation. If the 1Bh opcode is used, then two dummy bytes must be clocked into the
device after the three address bytes. If the 0Bh opcode is used, then a single dummy byte must be clocked in after
the address bytes.
After the three address bytes (and the dummy bytes or byte if using opcodes 1Bh or 0Bh) have been clocked in,
additional clock cycles will result in data being output on the SO pin. The data is always output with the MSB of a
byte first. When the last byte (0FFFFFh) of the memory array has been read, the device will continue reading back
at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array
to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS
pin can be deasserted at any time and does not require that a full byte of data be read.
Atmel AT25DF081A
MSB
HIGH-IMPEDANCE
Read Array – 1Bh Opcode
0
0
0
1
0
2
OPCODE
1
3
1
4
0
5
1
6
1
7
MSB
A
8
A
9
ADDRESS BITS A23-A0
A
10 11
A
A
12
CLK
A
should be reserved to systems employing the Atmel RapidS
A
29 30
A
A
31 32
MSB
X
RDLF
X
33
DON'T CARE
X
34
. The 1Bh opcode allows the highest read performance pos-
CLK
X
35
X
36
, and the 03h opcode can be used for lower frequency
X
37 38
X
X
39
MSB
X
40
X
41
DON'T CARE
X
42 43
X
X
44
X
45
X
46
X
47 48
MAX
MSB
D
; however, use of the 1Bh
D
49
DATA BYTE 1
D
50 51
D
D
52
D
53
D
54
8715B–SFLSH–8/10
TM
D
55 56
MSB
protocol.
D
D