AT25DF081-SSHN-B Atmel, AT25DF081-SSHN-B Datasheet
AT25DF081-SSHN-B
Specifications of AT25DF081-SSHN-B
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AT25DF081-SSHN-B Summary of contents
Page 1
... Ultra Thin DFN ( 0.6 mm) – 11-ball dBGA (WLCSP) 1. Description The AT25DF081 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shad- owed from Flash memory into embedded or external RAM for execution. The flexible ...
Page 2
... Specifically designed for use in 1.8-volt systems, the AT25DF081 supports read, program, and erase operations with a supply voltage range of 1.65V to 1.95V. No separate voltage is required for programming and erasing. ...
Page 3
... GROUND: The ground reference for the power supply. GND should be connected to the system GND ground. 3674E–DFLASH–8/08 for more details on protection features and the pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be attempted. AT25DF081 Asserted State Type Low Input Input Input ...
Page 4
... HOLD 4. Memory Array To provide the greatest flexibility, the memory array of the AT25DF081 can be erased in four lev- els of granularity including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations ...
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... – 004000h 32KB 4KB 003F – 003000h 4KB 002F – 002000h 4KB 001F – 001000h 4KB 000F – 000000h AT25DF081 Page Program Detail 1-256 Byte Page Program Range (02h Command) 256 Bytes – 00h 256 Bytes h– 00h 256 Bytes – ...
Page 6
... SPI Master. All opcode, address, and data bytes are transferred with the most significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT25DF081 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted) ...
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... Use Write Status Register command 3Ch 0011 1100 3 05h 0000 0101 0 01h 0000 0001 0 9Fh 1001 1111 0 B9h 1011 1001 0 ABh 1010 1011 0 AT25DF081 Dummy Bytes Data Bytes ...
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... The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 7-1. Read Array – 0Bh Opcode SCK OPCODE MSB HIGH-IMPEDANCE SO Figure 7-2. Read Array – 03h Opcode CS SCK SI MSB HIGH-IMPEDANCE SO AT25DF081 ADDRESS BITS A23- ...
Page 9
... The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly programming error arises, it will be indicated by the EPE bit in the Status Register. 3674E–DFLASH–8/08 time to determine if the data bytes have finished programming AT25DF081 . PP “Protect Sector” on page 13), 9 ...
Page 10
... Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is deas- serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. AT25DF081 ...
Page 11
... While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput recommended that the Status Regis- 3674E–DFLASH–8/08 time to determine if the device has finished erasing. At BLKE Block Erase SCK OPCODE MSB HIGH-IMPEDANCE SO . CHPE AT25DF081 ADDRESS BITS A23- MSB ...
Page 12
... CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. AT25DF081 12 time to determine if the device has finished erasing. At CHPE ...
Page 13
... Sector Protection Register corresponding to the physical sector addressed by A23- 3674E–DFLASH–8/08 Write Disable CS 0 SCK MSB HIGH-IMPEDANCE SO Sector Protection Register Values Sector Protection Status Sector is unprotected and can be programmed and erased. Sector is protected and cannot be programmed or erased. This is the default state. AT25DF081 OPCODE ...
Page 14
... Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical “0”. AT25DF081 14 for more details). If the Sector Protection Registers are locked, then any attempts to ...
Page 15
... If the Sector Protection Registers are locked, then any attempts to Unprotect Sector SCK OPCODE MSB HIGH-IMPEDANCE SO page 22 for command execution details). The Write Status Register com- AT25DF081 “Status Register Commands” ADDRESS BITS A23- MSB Table 9-2 details the conditions ...
Page 16
... Global Protect and keep the SPRL bit in the logical “0” state. The SPRL bit can, of course, be changed to a logical “1” by writing an FFh if software-locking or hardware-locking is desired along with the Global Protect. AT25DF081 16 Valid SPRL and Global Protect/Unprotect Conditions New ...
Page 17
... Status Register format and what values can be Read Sector Protection Register – Output Data Sector Protection Register Value 00h Sector Protection Register value is 0 (sector is unprotected). FFh Sector Protection Register value is 1 (sector is protected). “Status Register Commands” on page 20 AT25DF081 for more details). 17 ...
Page 18
... When changing the SPRL bit to a logical “1” from a logical “0” also possible to perform a Global Protect or Global Unprotect at the same time by writing the appropriate values into bits and 2 of the Status Register. AT25DF081 18 Read Sector Protection Register ...
Page 19
... Can be modified from Hardware 1 Locked Locked 0 Can be modified from Software 1 Can be modified from Locked AT25DF081 Sector (1) n Unprotected Protected Sector Protection Registers Unlocked and modifiable using the Protect and Unprotect Sector commands. Global Protect and Unprotect can also be performed. Locked in current state. Protect and Unprotect Sector commands will be ignored ...
Page 20
... WEL Write Enable Latch Status 0 RDY/BSY Ready/Busy Status Notes: 1. Only bit 7 of the Status Register will be modified when using the Write Status Register command. 2. R/W = Readable and writeable R = Readable only AT25DF081 20 (2) Type Description 0 Sector Protection Registers are unlocked (default). R/W 1 Sector Protection Registers are locked ...
Page 21
... Protect Sector, Unprotect Sector, or Write Status Register commands. The WEL bit defaults to the logical “0” state after a device power-up or reset. In addition, the WEL bit will be reset to the logical “0” state automati- cally under the following conditions: 3674E–DFLASH–8/08 AT25DF081 21 ...
Page 22
... The values of bits and 2 and the state of the SPRL bit before the Write Status Register command was executed (the prior state of the SPRL bit) will determine whether or not a Global Protect or Global Unprotect will be perfomed. Please refer to the “Global Protect/Unprotect” section on AT25DF081 ...
Page 23
... SO pin and no data will be output. As indicated in the JEDEC standard, reading the Extended Device Information String Length and any subsequent data is optional. 3674E–DFLASH–8/08 Write Status Register Format Bit 6 Bit 5 Bit 4 X Global Protect/Unprotect SCK OPCODE MSB HIGH-IMPEDANCE SO AT25DF081 Bit 3 Bit 2 Bit STATUS REGISTER MSB Bit ...
Page 24
... Manufacturer and Device ID Details Data Type Bit 7 Bit 6 Bit 5 Manufacturer Family Code Device ID (Part Sub Code Device ID (Part Figure 11-1. Read Manufacturer and Device ID CS SCK SI SO AT25DF081 24 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 JEDEC Assigned Code Density Code Product Version Code ...
Page 25
... The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-Down mode. Figure 11-2. Deep Power-Down 3674E–DFLASH–8/ SCK OPCODE MSB HIGH-IMPEDANCE SO Active Current I CC Standby Mode Current Deep Power-Down Mode Current AT25DF081 . EDPD t EDPD ...
Page 26
... If the complete opcode is not clocked in before the CS pin is deasserted the CS pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down mode. Figure 11-3. Resume from Deep Power-Down AT25DF081 26 and return to the standby mode. After the device RDPD ...
Page 27
... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. Figure 11-4. Hold Mode CS SCK HOLD 3674E–DFLASH–8/08 Hold Hold AT25DF081 Hold 27 ...
Page 28
... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT25DF081 -40° +85° C 1.65V to 1.95V Min Typ Max 25 ...
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... Chip Select High to Standby Mode RDPD Notes: 1. Not 100% tested (value guaranteed by design and characterization load at 66 MHz load at 60 MHz. 3. Only applicable as a constraint for the Write Status Register command when SPRL = 1. 3674E–DFLASH–8/08 AT25DF081 Min Max Units 66 MHz 33 MHz 6 ...
Page 30
... Parameter t Minimum V to Chip Select Low Time VCSL CC t Power-up Device Delay Before Program or Erase Allowed PUW V Power-On Reset Voltage POR 12.7 Input Test Waveforms and Measurement Levels 12.8 Output Test Load AT25DF081 30 4-Kbyte 32-Kbyte 64-Kbyte 0. DRIVING V CC LEVELS 0. < (10% to 90%) ...
Page 31
... CSLS SCK MSB HIGH-IMPEDANCE SO Figure 13-2. Serial Output Timing CS SCK Figure 13-3. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO 3674E–DFLASH–8/08 t CSLH t t SCKH SCKL t DH LSB HHH HLS t HLH AT25DF081 t CSH t CSHH t CSHS MSB SCKH SCKL DIS t HHS 31 ...
Page 32
... SCK t HHH HOLD SI t HLQZ SO Figure 13-5. WP Timing for Write Status Register Command When SPRL = WPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER OPCODE HIGH-IMPEDANCE SO AT25DF081 32 t HLS t HLH t HHQX t WPH LSB OF WRITE STATUS REGISTER DATA BYTE t HHS MSB MSB OF NEXT OPCODE ...
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... Atmel Designator Product Family Device Density 08 = 8-megabit Interface 1 = Serial 14.2 Green Package Options (Pb/Halide-free/RoHS Compliant) Ordering Code Package AT25DF081-SSHN-B 8S1 AT25DF081-SSHN-T AT25DF081-MHN-Y 8MA1 AT25DF081-MHN-T AT25DF081-UUN-T 11U1 Notes: 1. The shipping carrier option code is not marked on the devices. 2. Please contact Atmel for 11-ball dBGA package outline drawing. ...
Page 34
... Green Package Options (Pb/Halide-free/RoHS Compliant) Ordering Code Package AT25DF081-WDT20N Bare Die AT25DF081-WDT11N AT25DF081-WBT11N Bumped Die Notes: 1. Die/wafer carrier option code is not marked on devices. 2. Please contact Atmel for minimum order requirements for bare die and bumped die options. AT25DF081 34 1 – Lead Finish Operating Voltage n/a 1 ...
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... These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R 3674E–DFLASH–8/ TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) AT25DF081 Ø Ø END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A1 0.10 – 0.25 DRAWING NO ...
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... UDFN E Pin TOP VIEW Pin #1 Notch (0.20 R) (Option BOTTOM VIEW L Package Drawing Contact: packagedrawings@atmel.com AT25DF081 36 SIDE VIEW A1 A 0.45 Option A Pin #1 1 Chamfer (C 0.35) SYMBOL TITLE 8MA1, 8-pad ( 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead ...
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... History Initial release Changed part number ordering code to reflect NiPdAu lead finish - Changed AT25DF081-SSU-1.8 to AT25DF081-SSH-1.8 - Changed AT25DF081-MU-1.8 to AT25DF081-MH-1.8 Added lead finish details to Ordering Information table Changed description from “1.8-volt Only Serial Firmware DataFlash” to “1.65-volt Minimum SPI Serial Flash” ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...