AT25DF081A-MH-T Atmel, AT25DF081A-MH-T Datasheet - Page 36

• Manufacturer Part Number: AT25DF081A-MH-T
• Description: IC FLASH 8MBIT SPI 8UDFN
• Manufacturer: Atmel

Specifications of AT25DF081A-MH-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 8M (4096 pages x 256 bytes)
• Speed: 100MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-UDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3
36
Write Status Register Byte 2
The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Status Register. Using
the Write Status Register Byte 2 command is the only way to modify the RSTE and SLE bits in the Status Register
during normal device operation, and the SLE bit can only be modified if the sector lockdown state has not been fro-
zen. Before the Write Status Register Byte 2 command can be issued, the Write Enable command must have been
previously issued to set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and the opcode of 31h must
be clocked into the device followed by one byte of data. The one byte of data consists of three don’t care bits, the
RSTE bit value, the SLE bit value, and three additional don’t care bits (see
that are sent to the device will be ignored. When the CS pin is deasserted, the RSTE and SLE bits in the Status
Register will be modified, and the WEL bit in the Status Register will be reset back to a logical “0”. The SLE bit will
only be modified if the Freeze Sector Lockdown State command has not been previously issued.
The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin
must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation,
the state of the RSTE and SLE bits will not change, and the WEL bit in the Status Register will be reset back to the
logical “0” state.
Table 11-4.
Figure 11-3. Write Status Register Byte 2
SCK
Atmel AT25DF081A
SO
CS
Bit 7
SI
X
Write Status Register Byte 2 Format
Bit 6
MSB
HIGH-IMPEDANCE
X
0
0
0
1
1
2
OPCODE
1
3
0
Bit 5
4
X
0
5
0
6
1
7
MSB
X
8
RSTE
STATUS REGISTER IN
Bit 4
X
9
X
10 11
BYTE 2
D
D
12
X
13
Bit 3
SLE
X
14 15
X
Bit 2
X
Bit 1
Table
X
11-4). Any additional data bytes
Bit 0
X
8715B–SFLSH–8/10