AT25DF081A-MH-T Atmel, AT25DF081A-MH-T Datasheet - Page 18

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AT25DF081A-MH-T

Manufacturer Part Number
AT25DF081A-MH-T
Description
IC FLASH 8MBIT SPI 8UDFN
Manufacturer
Atmel
Datasheet

Specifications of AT25DF081A-MH-T

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
8M (4096 pages x 256 bytes)
Speed
100MHz
Interface
SPI, RapidS
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-UDFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
9.2
18
Write Disable
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical
"0" state. With the WEL bit reset, all Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lock-
down, Freeze Sector Lockdown State, Program OTP Security Register, and Write Status Register commands will
not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to the WEL bit
section of the Status Register description.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will
be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The
complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deas-
serted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the
state of the WEL bit will not change.
Figure 9-2.
SCK
Atmel AT25DF081A
SO
CS
SI
Write Disable
MSB
HIGH-IMPEDANCE
0
0
0
1
0
2
OPCODE
0
3
0
4
1
5
0
6
0
7
8715B–SFLSH–8/10

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