5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 121

• Manufacturer Part Number: 5M240ZT100C5N
• Description: IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M240ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 192
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
January 2011 Altera Corporation
Sector Erase (Byte Address Triggered)
This sector erase operation is triggered by defining a 7- to 10-bit byte address for each
sector depending on the memory size. The trigger address for each sector is entered
on page 4 of the ALTUFM MegaWizard Plug-In Manager. When a write operation is
executed targeting this special byte address location, the UFM sector that contains
that byte address location is erased. This sector erase operation is automatically
followed by a write of the intended write byte to that address. The default byte
address location for UFM Sector 0 erase is address 0×00. The default byte address
location for UFM Sector 1 erase is [(selected memory size)/2]. You can specify another
byte location as the trigger-erase addresses for each sector.
This sector erase operation supports up to eight UFM blocks or serial EEPROMs on
the I
Sector Erase (A
This sector erase operation uses the received A
between an erase or read/write operation. This slave operation decoding occurs when
the master transmits the slave address after generating the start condition. If the A
received by the UFM slave is 1, the sector erase operation is selected. If the A
received is 0, the read/write operation is selected. While this reserves the A
erase or read/write operation bit, the A
address the UFM. With this erase option, there can be up to four UFM slaves cascaded
on the bus for 1-Kbit and 2-Kbit memory sizes. Only two UFM slaves can be cascaded
on the bus for 4-Kbit memory size, because A
bit (MSB) of the byte address. After the slave acknowledges the slave address and its
erase or read/write operation bit, the master can transfer any byte address within the
sector that must be erased. The internal UFM sector erase operation only begins after
the master generates a stop condition.
using the A
Figure 7–14. Sector Erase Sequence Indicated Using the A
If the ALTUFM_I2C megafunction is write-protected (WP=1), the slave does not
acknowledge the byte address (that indicates the UFM sector to be erased) sent in by
the master. The master should then send a stop condition to terminate the transfer and
the sector erase operation will not be executed.
Note to
(1) A
2
a read or write operation.
C bus. This sector erase operation requires acknowledge polling.
2
= 0 indicates a read/write operation is executed in place of an erase. Here, the R/W bit determines whether it is
Figure
2
7–14:
bit of the slave address.
2
Triggered)
S – Start Condition
P – Stop Condition
A – Acknowledge
S
Slave Address
A
2
= '1'
'0' (write) (1)
R/W
Figure 7–14
0
and A
A
0
Byte Address
2
of the slave address becomes the ninth
1
slave address bit to distinguish
bits still act as slave address bits to
shows the sector erase sequence
2
Bit of the Slave Address
From Master to Slave
From Slave to Master
A
P
MAX V Device Handbook
2
2
bit as an
bit
2
7–19
bit