5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 93

• Manufacturer Part Number: 5M240ZT100C5N
• Description: IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M240ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 192
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5: Using MAX V Devices in Multi-Voltage Systems
Recommended Operating Conditions for 5.0-V Compatibility
Recommended Operating Conditions for 5.0-V Compatibility
December 2010 Altera Corporation
As shown in
The values usually shown in the data sheets reflect typical operating conditions.
Subtract 20% from the data sheet value for guard band. When you subtract the 20%
from the previous example, the R
Select R
the above device has a maximum I
V
(V
Equation 5–2.
This analysis assumes worst-case conditions. If your system does not see a wide
variation in voltage-supply levels, you can adjust these calculations accordingly.
Because 5.0-V device tolerance in MAX V devices requires the use of the I/O clamp,
and this clamp is activated only after power-up, 5.0-V signals may not be driven into
the device until it is configured. The I/O clamp diode is only supported in the
5M1270Z and 5M2210Z devices’ I/O Bank 3. You must have an external protection
diode for the other I/O banks for the 5M1270Z and 5M2210Z devices and all the I/O
pins in the 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z devices.
As mentioned earlier, a 5.0-V tolerance can be supported with the I/O clamp diode
enabled with external series/pull-up resistance. To guarantee long term reliability of
the device’s I/O buffer, there are restrictions on the signal duty cycle that drive the
MAX V I/O, which is based on the maximum clamp current.
maximum signal duty cycle for the 3.3-V V
capability.
Table 5–3. Maximum Signal Duty Cycle
Notes to
(1) V
(2) The I
IN
CC
= V
) is 5.5 V, calculate value of R
IN
is the voltage at the package pin.
CCIO
2
Table
CH
so that the MAX V device’s I
V
is calculated with a 3.3-V V
IN
+ 0.7 V = 3.7 V. Given that the maximum supply load of a 5.0-V device
5–3:
(V)
4.0
4.1
4.2
4.3
4.4
4.5
4.6
Figure
(1)
5–5, R
R
2
=
1

----------------------------------------------------------------------------------- -
= 5.0 V/135 mA.
5.5 V 3.7 V
CCIO
. A higher V
1
–
2
value is 30.
OH
as follows:
OH
of 8 mA, given the I/O clamp diode,
I
CH
8 mA

CCIO
11.67
18.33
25.00
31.67
38.33
45.00
(mA)
specification is not violated. For example, if
–
5.00

CCIO
8 mA
value will have a lower I
(2)
given a PCI clamp current-handling

30 

=
194 
CH
Table 5–3
value with the same V
Max Duty Cycle (%)
MAX V Device Handbook
100
90
50
30
17
10
5
lists the
IN
.
5–7