5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 133

• Manufacturer Part Number: 5M240ZT100C5N
• Description: IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M240ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 192
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
January 2011 Altera Corporation
WREN (Write Enable)
The interface is powered-up in the write disable state. Therefore, WEN in the status
register (refer to
place, WREN must be issued to set WEN in the status register to 1. If the interface is in
read-only mode, WREN does not have any effect on WEN, because the status register does
not exist. After WEN is set to 1, it can be reset by the WRDI instruction; the WRITE and
SECTOR-ERASE instructions will not reset the WEN bit. WREN is issued through the
following sequence, as shown in
1. nCS is pulled low.
2. Opcode 00000110 is transmitted into the interface to set WEN to 1 in the status
3. After the transmission of the eighth bit of WREN, the interface is in wait state
4. nCS is pulled back to high.
Figure 7–28. WREN Operation Sequence
register.
(waiting for nCS to be pulled back to high). Any transmission after this is ignored.
Table
7–11) is 0 at power-up. Before any write is allowed to take
SCK
nCS
SI
SO
Figure
MSB
0
1
High Impedance
7–28:
Instruction
2
8-bit
06
3
H
4
5 6 7
MAX V Device Handbook
7–31