5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 131

• Manufacturer Part Number: 5M240ZT100C5N
• Description: IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M240ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 192
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
January 2011 Altera Corporation
4. nCS is pulled back to high.
For SPI Base mode, the SE instruction erases UFM sector 0. Because there are no
choices of UFM sectors to be erased, there is no address component to this instruction.
The SE operation is always done through the following sequence in SPI Base mode:
1. nCS is pulled low.
2. Opcode 00100000 is transmitted into the interface.
3. nCS is pulled back to high.
Figure 7–25. SECTOR-ERASE Operation Sequence for Extended Mode
Figure 7–26
Figure 7–26. SECTOR_ERASE Operation Sequence for Base Mode
shows the SECTOR-ERASE operation sequence for Base mode.
SCK
nCS
SI
SO
SCK
nCS
SI
SO
MSB
0
1
Instruction
2
8-bit
20
3
MSB
H
0
4
1
Instruction
5 6 7
2
8-bit
20
High Impedance
3
H
MSB
4
8
5 6 7
9 10 11
High Impedance
Address
16-bit
20 21 22 23
MAX V Device Handbook
7–29