5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 85

• Manufacturer Part Number: 5M240ZT100C5N
• Description: IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M240ZT100C5N

• Cpld Type: FLASH
• No. Of Macrocells: 192
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Rohs Compliant: Yes
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 240
• Number Of Macrocells: 192
• Number Of Gates: -
• Number Of I /o: 79
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4: Hot Socketing and Power-On Reset in MAX V Devices
Power-On Reset Circuitry
Figure 4–4. ESD Protection During Negative Voltage Zap
Power-On Reset Circuitry
December 2010 Altera Corporation
Power-Up Characteristics
When the I/O pin receives a negative ESD zap at the pin that is less than –0.7 V (0.7 V
is the voltage drop across a diode), the intrinsic
P-Substrate/N+ drain diode is forward biased. Therefore, the discharge ESD current
path is from GND to the I/O pin, as shown in
MAX V devices have POR circuits to monitor the V
during power up. The POR circuit monitors these voltages, triggering download from
the non-volatile configuration flash memory block to the SRAM logic, maintaining the
tri-state of the I/O pins (with weak pull-up resistors enabled) before and during this
process. When the MAX V device enters user mode, the POR circuit releases the I/O
pins to user functionality. The POR circuit of the MAX V device does not monitor the
V
When power is applied to a MAX V device, the POR circuit monitors V
begins SRAM download at 1.55 V for MAX V devices. From this voltage reference, the
SRAM download and entry into user mode takes 200 to 450 µs maximum, depending
on your device density. This period of time is specified as t
timing section of the
Entry into user mode is gated by whether all the V
sufficient operating voltage. If V
device enters user mode within the t
than t
banks are powered.
CCINT
CONFIG
voltage level after the device enters into user mode.
I/O
after V
CCINT
GND
DC and Switching Characteristics for MAX V Devices
Source
Drain
Drain
Source
, the device does not enter user mode until 2 µs after all V
PMOS
NMOS
CCINT
Gate
Gate
CONFIG
and V
P-Substrate
specifications. If V
CCIO
Figure
N+
N+
are powered simultaneously, the
CCIO
D
S
CCINT
GND
I/O
G
4–4.
banks are powered with
and V
CONFIG
CCIO
CCIO
in the power-up
is powered more
voltage levels
MAX V Device Handbook
CCINT
chapter.
and
CCIO
4–5