5M240ZT100C5N Altera, 5M240ZT100C5N Datasheet - Page 40

no-image

5M240ZT100C5N

Manufacturer Part Number
5M240ZT100C5N
Description
IC CPLD FLASH, 192, 7.5NS, 118.3MHZ, TQFP-100
Manufacturer
Altera
Series
MAX Vr

Specifications of 5M240ZT100C5N

Cpld Type
FLASH
No. Of Macrocells
192
No. Of I/o's
79
Propagation Delay
7.5ns
Global Clock Setup Time
4.6ns
Frequency
118.3MHz
Supply Voltage Range
1.71V To 1.89V
Rohs Compliant
Yes
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
240
Number Of Macrocells
192
Number Of Gates
-
Number Of I /o
79
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
5M240ZT100C5N
Manufacturer:
ALTERA45
Quantity:
895
Part Number:
5M240ZT100C5N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
5M240ZT100C5N
Manufacturer:
ALTERA
0
Part Number:
5M240ZT100C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
5M240ZT100C5N
0
Part Number:
5M240ZT100C5N+CODE
Manufacturer:
ALTERA
0
2–28
MAX V Device Handbook
I/O Blocks
1
The IOEs are located in I/O blocks around the periphery of the MAX V device. There
are up to seven IOEs per row I/O block and up to four IOEs per column I/O block.
Each column or row I/O block interfaces with its adjacent LAB and MultiTrack
interconnect to distribute signals throughout the device. The row I/O blocks drive
row, column, or DirectLink interconnects. The column I/O blocks drive column
interconnects.
5M40Z, 5M80Z, 5M160Z, and 5M240Z devices have a maximum of five IOEs per row
I/O block.
Figure 2–20
Figure 2–20. Row I/O Block Connection to the Interconnect
Note to
(1) Each of the seven IOEs in the row I/O block can have one data_out or fast_out output, one OE output, and
one data_in input.
Figure
LAB Local
Interconnect
2–20:
shows how a row I/O block connects to the logic array.
R4 Interconnects
to Adjacent LAB
Interconnect
Direct Link
LAB
from Adjacent LAB
Interconnect
C4 Interconnects
Direct Link
data_in[6..0]
LAB Column
clock [3..0]
I/O Block Local
Interconnect
(Note 1)
December 2010 Altera Corporation
data_out
fast_out
7
7
7
7
[6..0]
[6..0]
[6..0]
OE
Chapter 2: MAX V Architecture
Row I/O Block
Contains up to
I/O Block
Seven IOEs
Row
I/O Structure

Related parts for 5M240ZT100C5N