H27UF081G1M-TPCB HYNIX SEMICONDUCTOR, H27UF081G1M-TPCB Datasheet - Page 10

• Manufacturer Part Number: H27UF081G1M-TPCB
• Description: IC, MEMORY, FLASH NAND 1GB, TSOP48
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H27UF081G1M-TPCB

• Access Time: 45ns
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Base Number: 27
• Interface: Serial
• Logic: RoHS Compliant
• Package / Case: TSOP
• Memory Type: Flash - NAND
• Memory Configuration: 128M X 8
• Rohs Compliant: Yes
• Memory Size: 1Gbit

Preliminary
HY27US(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby.
Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not
affect bus operations.
2.1 Command Input.
Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip
Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising
edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin
must be high. See figure 5 and table 12 for details of the timings requirements. Command codes are always applied on
IO7:0, disregarding the bus configuration (X8/X16).
2.2 Address Input.
Address Input bus operation allows the insertion of the memory address. Four cycles are required to input the
addresses for the 1Gbit devices. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command
Latch Enable low and Read Enable high and latched on the rising edge of Write Enable. Moreover for commands that
starts a modify operation (write/erase) the Write Protect pin must be high. See figure 6 and table 12 for details of the
timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration (X8/X16).
In addition, addresses over the addressable space are disregarded even if the user sets them during command inser-
tion.
2.3 Data Input.
Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and
timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command
Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure
7 and table 12 for details of the timings requirements.
2.4 Data Output.
Data Output bus operation allows to read data from the memory array and to check the status register content, the
lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write
Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 13 to 17 and table 12 for details
of the timings requirements.
2.5 Write Protect.
Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not
start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the pro-
tection even during the power up.
2.6 Standby.
In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
Rev 0.2 / May. 2007
10