UPD78F0886GA(A)-GAM-AX NEC, UPD78F0886GA(A)-GAM-AX Datasheet - Page 49

8BIT MCU, 60K FLASH, 3KB RAM, CAN

UPD78F0886GA(A)-GAM-AX

Manufacturer Part Number
UPD78F0886GA(A)-GAM-AX
Description
8BIT MCU, 60K FLASH, 3KB RAM, CAN
Manufacturer
NEC
Datasheet

Specifications of UPD78F0886GA(A)-GAM-AX

Controller Family/series
UPD78F
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm Channels
6
Digital Ic Case Style
LQFP
Core Size
8bit
Program Memory Size
60KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
[Instruction format]
[Operation]
[Operand]
[Flag]
[Description]
[Description example]
MOV
• The contents of the source operand (src) specified by the 2nd operand are transferred to the destination
• No interrupts are acknowledged between the MOV PSW, #byte instruction/MOV PSW, A instruction and the
MOV A, #4DH; 4DH is transferred to the A register.
Note Except r = A
PSW, #byte and PSW,
A operands
operand (dst) specified by the 1st operand.
next instruction.
Mnemonic
Z
×
MOV
AC
×
r, #byte
saddr, #byte
sfr, #byte
A, r
r, A
A, saddr
saddr, A
A, sfr
sfr, A
A, !addr16
!addr16, A
PSW, #byte
dst ← src
MOV dst, src
CY
×
Operand(dst,src)
CHAPTER 5 EXPLANATION OF INSTRUCTIONS
All other operand
combinations
User's Manual U12326EJ4V0UM
Z
Note
Note
AC
Mnemonic
CY
MOV
A, PSW
PSW, A
A, [DE]
[DE], A
A, [HL]
[HL], A
A, [HL+byte]
[HL+byte], A
A, [HL+B]
[HL+B], A
A, [HL+C]
[HL+C], A
Operand(dst,src)
Byte Data Transfer
Move
49

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