AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 10

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2
10
System Address Map
The SoC processor supports 64GB (36 bit) of addressable memory space and 64 KB+3
of addressable I/O space. There is a programmable memory address space under the
1 MB region, which is divided into regions, which can be individually controlled with
programmable attributes such as Disable, Read/Write, Write Only, or Read Only.
Attribute programming is described in the Register Description section. This section
focuses on how the memory space is partitioned and what the separate memory
regions are used. I/O address space has simpler mapping and is explained near the
end of this section.
Addressing of greater than 4 GB is allowed on either the DMI Interface. The SoC
processor supports a maximum of 8GB of DRAM. No DRAM memory will be accessible
above 16 GB. DRAM capacity is limited by the number of address pins available. There
is no hardware lock to stop someone from inserting more memory than is
addressable.
When running in internal graphics mode, writes to GMADR range linear range are
supported. Write accesses to linear regions are supported from DMI. Write accesses to
tileX and tileY regions (defined via fence registers) are not supported from DMI.
GMADR read accesses are not supported from DMI.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI Interface. The exception to this rule is VGA ranges, which may be
mapped to DMI or to the internal graphics device (IGD). In the absence of more
specific references, cycle descriptions referencing PCI should be interpreted as the
DMI Interface/PCI, while cycle descriptions referencing IGD are related to the internal
graphics device. Processor does not remap APIC or any other memory spaces above
TOLUD (Top of Low Usable DRAM). The TOLUD register is set to the appropriate value
by BIOS. The reclaimbase/reclaimlimit registers remap logical accesses bound for
addresses above 4G onto physical addresses that fall within DRAM.
The Address Map includes a number of programmable ranges:
Device 0:
PXPEPBAR – Egress port registers. Necessary for setting up VC1 as an isochronous
channel with fixed arbitration. (4KB window)
MCHBAR – Memory mapped range for internal MCH registers. For example, memory
buffer register controls. (16KB window)
W
W1C
Item
Write-only. These bits may be written by software, but will always return
zeros when read. They are used for write side-effects. Any data written to
these registers cannot be retrieved.
Write 1 to Clear-only. These bits may be cleared by software by writing a
1. Writing a 0 has no effect. The state of the bits cannot be read directly.
The states of such bits are tracked outside the CPU and all read transactions
to the address of such bits are routed to the other agent. Write transactions
to these bits go to both agents.
Definition
Processor Configuration Registers
Datasheet