AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 32

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

32
Bit
7
6
5
4
3
2
1
Access
RW
RO
RO
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
0b
1b
1b
RST/
PWR
Core
Core
Core
Core
Core
Core
Core
registers. The error status is reported in the
ERRSTS, PCISTS, and DMIUEST registers.
0: The SERR message is not generated by
the CPU Uncore for Device 0.
Note that this bit only controls SERR
messaging for the Device 0. The control bits
are used in a logical OR manner to enable
the SERR DMI message mechanism.
Address/Data Stepping Enable
(ADSTEP):
in the CPU Uncore, and this bit is hardwired
to 0. Writes to this bit position have no
effect.
Parity Error Enable (PERRE):
Controls whether or not the Master Data
Parity Error bit in the PCI Status register can
bet set.
0: Master Data Parity Error bit in PCI Status
register can NOT be set.
1: Master Data Parity Error bit in PCI Status
register CAN be set.
VGA Palette Snoop Enable (VGASNOOP):
and it is hardwired to a 0. Writes to this bit
position have no effect.
Memory Write and Invalidate Enable
(MWIE):
write and invalidate commands. This bit is
therefore hardwired to 0. Writes to this bit
position will have no effect.
Special Cycle Enable (SCE):
and it is hardwired to a 0. Writes to this bit
position have no effect.
Bus Master Enable (BME):
master on the backbone. This bit is
hardwired to a "1". Writes to this bit position
have no effect.
Memory Access Enable (MAE):
main memory. This bit is not implemented
and is hardwired to 1. Writes to this bit
position have no effect.
Address/data stepping is not implemented
The CPU Uncore does not implement this bit
The CPU Uncore will never issue memory
The CPU Uncore does not implement this bit
The CPU Uncore is always enabled as a
The CPU Uncore always allows access to
Processor Configuration Registers
Description
Datasheet