AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 55

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.5.29
Datasheet
ESMRAMC - Extended System Management RAM Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MB.
2:1
Bit
7
6
5
4
3
Access
RW/L
RW/L
RWC
RO
RO
RO
Default
Value
00b
0b
0b
1b
1b
1b
RST/
PWR
Core
Core
Core
Core
Core
Core
0/0/0/PCI
9Eh
38h
8 bits
RW/L; RWC; RO;
Enable High SMRAM (H_SMRAME):
above 1 MB or below 1 MB) When G_SMRAME is
1 and H_SMRAME is set to 1, the high SMRAM
memory space is enabled. SMRAM accesses
within the range 0FEDA0000h to 0FEDBFFFFh
are remapped to DRAM addresses within the
range 000A0000h to 000BFFFFh. Once D_LCK
has been set, this bit becomes read only.
Invalid SMRAM Access (E_SMERR):
defined memory ranges in Extended SMRAM
(High Memory and T-segment) while not in SMM
space and with the D-OPEN bit = 0. It is
software's responsibility to clear this bit. The
software must write a 1 to this bit to clear it.
SMRAM Cacheable (SM_CACHE):
This bit is forced to '1' by the CPU Uncore.
L1 Cache Enable for SMRAM (SM_L1):
This bit is forced to '1' by the CPU Uncore.
L2 Cache Enable for SMRAM (SM_L2):
TSEG Size (TSEG_SZ):
enabled. Memory from the top of DRAM space is
partitioned away so that it may only be accessed
by the processor interface and only then when
the SMM bit is set in the request packet. Non-
SMM accesses to this memory region are sent to
DMI when the TSEG memory block is enabled.
00:1MB Tseg. (TOLUD - GTT Graphics Memory
Size - Graphics Stolen Memory Size - 1M) to
(TOLUD - GTT Graphics Memory Size - Graphics
Stolen Memory Size).
01:2 MB Tseg (TOLUD - GTT Graphics Memory
Size - Graphics Stolen Memory Size - 2M) to
(TOLUD - GTT Graphics Memory Size - Graphics
Controls the SMM memory space location (i.e.
This bit is set when CPU has accessed the
This bit is forced to '1' by the CPU Uncore.
Selects the size of the TSEG memory block if
Description
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