P89LPC9103FTK NXP Semiconductors, P89LPC9103FTK Datasheet - Page 37

• Manufacturer Part Number: P89LPC9103FTK
• Description: MCU 8BIT 80C51 1K FLASH, HVSON-10
• Manufacturer: NXP Semiconductors

Specifications of P89LPC9103FTK

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 8
• Program Memory Size: 1KB
• Ram Memory Size: 128Byte
• Cpu Speed: 18MHz
• Oscillator Type: Internal Only
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant

NXP Semiconductors
P89LPC9102_9103_9107_3
Product data sheet
8.18.4 Mode 3
8.18.5 Baud rate generator and selection
8.18.6 Framing error
8.18.7 Break detect
8.18.8 Double buffering
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in
section
The P89LPC9103/9107 enhanced UART has an independent Baud Rate Generator. The
baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0
SFRs which together form a 16-bit baud rate divisor value that works in a similar manner
as Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing
functions.
The UART can use either Timer 1 or the baud rate generator output (see
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses CCLK.
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is logic 1, framing errors can be made available in SCON.7, respectively. If SMOD0 is
logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are set up
when SMOD0 is logic 0.
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device.
The UART has a transmit double buffer that allows buffering of the next character to be
written to SBUF while the first character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SnBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
Fig 15. Baud rate sources for UART (Modes 1, 3)
Section 8.18.5 “Baud rate generator and
baud rate generator
timer 1 overflow
(PCLK-based)
(CCLK-based)
Rev. 03 — 10 July 2007
8-bit microcontrollers with two-clock accelerated 80C51 core
2
SMOD1 = 1
SMOD1 = 0
th
P89LPC9102/9103/9107
data bit, and a stop bit (logic 1). In fact, Mode 3 is
selection”).
SBRGS = 0
SBRGS = 1
baud rate modes 1 and 3
© NXP B.V. 2007. All rights reserved.
Figure
002aaa978
15). Note
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