P89LPC9103FTK NXP Semiconductors, P89LPC9103FTK Datasheet - Page 45

• Manufacturer Part Number: P89LPC9103FTK
• Description: MCU 8BIT 80C51 1K FLASH, HVSON-10
• Manufacturer: NXP Semiconductors

Specifications of P89LPC9103FTK

• Controller Family/series: (8051) 8052
• Core Size: 8bit
• No. Of I/o's: 8
• Program Memory Size: 1KB
• Ram Memory Size: 128Byte
• Cpu Speed: 18MHz
• Oscillator Type: Internal Only
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant

NXP Semiconductors
P89LPC9102_9103_9107_3
Product data sheet
9.4.5 Dual channel, continuous conversion mode
9.4.6 Single step mode
9.5.1 Timer triggered start
9.5.2 Start immediately
9.5 Conversion start modes
9.6 Boundary limits interrupt
9.7 DAC output to a port pin with high output impedance
9.8 Clock divider
This is a variation of the auto scan continuous conversion mode where conversion occurs
on two user-selectable inputs. The result of the conversion of the first channel is placed in
result register, AD1DAT0. The result of the conversion of the second channel is placed in
result register, AD1DAT1. The first channel is again converted and its result stored in
AD1DAT2. The second channel is again converted and its result placed in AD1DAT3. An
interrupt is generated, if enabled, after every set of four conversions (two conversions per
channel).
This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any
combination of the four input channels can be selected for conversion. After each channel
is converted, an interrupt is generated, if enabled, and the A/D waits for the next start
condition. May be used with any of the start modes.
An A/D conversion is started by the overflow of Timer 0. Once a conversion has started,
additional Timer 0 triggers are ignored until the conversion has completed. The Timer
triggered start mode is available in all A/D operating modes.
Programming this mode immediately starts a conversion. This start mode is available in all
A/D operating modes.
The A/D converter has both a high and low boundary limit register. After the four MSBs
have been converted, these four bits are compared with the four MSBs of the boundary
high and low registers. If the four MSBs of the conversion are outside the limit an interrupt
will be generated, if enabled. If the conversion result is within the limits, the boundary
limits will again be compared after all 8 bits have been converted. An interrupt will be
generated, if enabled, if the result is outside the boundary limits. The boundary limit may
be disabled by clearing the boundary limit interrupt enable.
The A/D converter’s DAC block can be output to a port pin. In this mode, the AD1DAT3
register is used to hold the value fed to the DAC. After a value has been written to the DAC
(written to AD1DAT3), the DAC output will appear on the channel 3 pin.
The A/D converter requires that its internal clock source be in the range of 500 kHz to
3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock
from 1 to 8 is provided for this purpose.
Rev. 03 — 10 July 2007
8-bit microcontrollers with two-clock accelerated 80C51 core
P89LPC9102/9103/9107
© NXP B.V. 2007. All rights reserved.
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