CS4954-CQ Cirrus Logic Inc, CS4954-CQ Datasheet - Page 16

• Manufacturer Part Number: CS4954-CQ
• Description: Digital Video Encoder IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4954-CQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Ic Function: Digital Video Encoder IC
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PROG_VS Register (0x0D). VSYNC can be de-
layed by thirteen lines or advanced by eighteen lines.
5.2.3. Vertical Timing
The CS4954/5 can be configured to operate in any
of four different timing modes: PAL, which is 625
vertical lines, 25 frames per second interlaced;
NTSC, which is 525 vertical lines, 30 frames per
second interlaced; and either PAL or NTSC in Pro-
gressive Scan, in which the display is non-inter-
laced.
CONTROL_0 Register (0x00).
The CS4954/5 conforms to standard digital decom-
pression dimensions and does not process digital
input data for the active analog video half lines as
they are typically in the over/underscan region of
televisions. 240 active lines total per field are pro-
cessed for NTSC, and 288 active lines total per
field are processed for PAL. Frame vertical dimen-
sions are 480 lines for NTSC and 576 lines for
PAL. Table 2 specifies active line numbers for both
NTSC and PAL. Refer to Figure 6 for HSYNC,
VSYNC and FIELD signal timing.
5.2.4. Horizontal Timing
HSYNC is used to synchronize the horizontal-in-
put-to-output timing in order to provide proper hor-
izontal alignment. HSYNC defaults to an input pin
following RESET but switches to an output in Mas-
ter Mode (CONTROL_0 [4] = 1). Horizontal tim-
ing is referenced to HSYNC transitioning low. For
active video lines, digital video input is to be ap-
plied to the V [7:0] inputs for 244 (NTSC) or for
264 (PAL) CLK periods following the leading
16
NTSC
PAL
NTSC Progressive-Scan
PAL Progressive-Scan
These
Mode
Table 2. Vertical Timing
modes
1, 3, 5, 7;
2, 4, 6, 8
are
Field
1, 3;
2, 4
NA
NA
selected
Active Lines
285-524
336-623
22-261;
23-310;
22-261
23-310
in
the
(falling) edge of HSYNC if the PROG_HS Regis-
ters are set to default values.
5.2.5. NTSC Interlaced
The CS4954/5 supports NTSC-M, NTSC-J and
PAL-M modes where there are 525 total lines per
frame and two fixed 262.5-line fields per frame and
30 total frames occurring per second. NTSC inter-
laced vertical timing is illustrated in Figure 7. Each
field consists of one line for closed caption, 240 ac-
tive lines of video, plus 21.5 lines of blanking.
VSYNC field one transitions low at the beginning
of line four and will remain low for three lines or
2574 pixel cycles (858 × 3). The CS4954/5 exclu-
sively reserves line 21 of field one for closed cap-
tion insertion. Digital video input is expected to be
delivered to the CS4954/5 V [7:0] pins for 240
lines beginning on active video lines 22 and con-
tinuing through line 261. VSYNC field two transi-
tions low in the middle of line 266 and stays low for
three line-times and transitions high in the middle
of line 269. The CS4954/5 exclusively reserves line
284 of field two for closed caption insertion. Video
input on the V [7:0] pins is expected between lines
285 through line 525.
5.2.6. PAL Interlaced
The CS4954/5 supports PAL modes B, D, G, H, I,
N, and Combination N, in which there are 625 total
lines per frame, two fixed 312.5 line fields per
frame, and 25 total frames per second. Figure 8 il-
lustrates PAL interlaced vertical timing. Each field
consists of 287 active lines of video plus 25.5 lines
of blanking.
VSYNC will transition low to begin field one and
will remain low for 2.5 lines or 2160 pixel cycles
(864 × 2.5). Digital video input is expected to be
delivered to the CS4954/5 V [7:0] pins for 287
lines beginning on active video line 24 and continu-
ing through line 310.
Field two begins with VSYNC transitioning low
after 312.5 lines from the beginning of field one.
CS4954 CS4955
DS278PP4