CS4954-CQ Cirrus Logic Inc, CS4954-CQ Datasheet - Page 32

• Manufacturer Part Number: CS4954-CQ
• Description: Digital Video Encoder IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4954-CQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Ic Function: Digital Video Encoder IC
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

If some of the 6 DACs are not used, it is strongly
recommended
CONTROL_4 register) in order to reduce the pow-
er dissipation.
Depending on the external resistor connected to the
ISET pin the output drive of the DACs can be
changed. There are two modes in which the DACs
should either be operated in. An external resistor of
4 k must be connected to the ISET pin.
The first mode is the high impedance mode
(LOW_IMP bit set to 0). The DAC outputs will
then drive a double terminated load of 300
will output a video signal which conforms to the
analog video specifications for NTSC and PAL.
External buffers will be needed if the DAC output
load differs from 300 .
The second mode is the low impedence mode
(LOW_IMP but set to 1). The DAC output will
then drive a double terminated load of 75
will output a video signal which conforms to the
analog video specifications for NTSC and PAL. No
external buffers are necessary, the ouputs can di-
rectly drive a television input.
Note that for power dissipation purposes it is not
always possible to have all the 6 DACs active at the
same time. Table 8 shows the maximum allowed
active DACs depending on the power supply and
low/high impedance modes. If less than 6 DACs
are allowed to be active the other ones must be
power down (see CONTROL_4 register).
32
SDA
SCL
Start
A
to
Address
power
1-7
Note: I
R/W
them
8
2
C transfers data always with MSB first, LSB last
ACK
9
down
Figure 26. I
1-7
(see
and
and
Data
2
C Protocol
8
8.
8.1.
The CS4954/5 host control interface can be config-
ured for I
CS4954/5 will default to I
RD and WR pins are both tied low at power up. The
RD and WR pins are active for 8-bit parallel oper-
ation only.
8.1.1. I
The CS4954/5 provides an I
ing the internal control and status registers. Exter-
nal pins are a bidirectional data pin (SDA) and a
serial input clock (SCL). The protocol follows the
I
shown in Figure 26. Note that this I
work in Slave Mode only - it is not a bus master.
SDA and SCL are connected via an external pull-
up resistor to a positive supply voltage. When the
bus is free, both lines are high. The output stages of
devices connected to the bus must have an open-
drain or open-collector in order to perform the
wired-AND function. Data on the I
Nominal Power
2
C specifications. A complete data transfer is
ACK
9
supply
PROGRAMMING
3.3V
3.3V
5.0V
5.0V
Host Control Interface
2
C Interface
Table 8. Maximum DAC Numbers
2
C or 8-bit parallel operation. The
1-7
High Impedance
High Impedance
Low Impedance
Low Impedance
Impedance
Low/High
8
Data ACK
mode
CS4954 CS4955
9
2
2
C operation when the
C interface for access-
2
maximum # of
C interface will
active DACs
Stop
2
P
C bus can be
DS278PP4
3
6
3
6