CS4954-CQ Cirrus Logic Inc, CS4954-CQ Datasheet - Page 21

• Manufacturer Part Number: CS4954-CQ
• Description: Digital Video Encoder IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4954-CQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Ic Function: Digital Video Encoder IC
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.4.
The CS4954/5 provides two different digital video
input modes that are selectable through the
IN_MODE bit in the CONTROL_0 Register.
In Mode 0 and upon RESET, the CS4954/5 de-
faults to output a solid color (one of a possible of
256 colors). The background color is selected by
writing the BKG_COLOR Register (0x08). The
colorspace of the register is RGB 3:3:2 and is unaf-
fected by gamma correction. The default color fol-
lowing RESET is blue.
In Mode 1 the CS4954/5 supports a single 8-bit
27 MHz CbYCrY source as input on the V [7:0]
pins. Input video timing can be ITU-R.BT601 mas-
ter or slave and ITU-R.BT656.
5.5.
The CS4954/5 supports a wide range of output for-
mats compatible with worldwide broadcast stan-
dards. These formats include NTSC-M, NTSC-J,
PAL-B/D/G/H/I, PAL-M, PAL-N, and PAL Com-
bination N (PAL-Nc) which is the broadcast stan-
dard used in Argentina. After RESET, the CS4954/5
defaults to NTSC-M operation with ITU R.BT 601
analog timing. NTSC-J can also be supported in the
Japanese format by turning off the 7.5 IRE pedestal
through the PED bit in the CONTROL_1 Register
(0x01).
DS278PP4
ITU R.BT656
DATA
Digital Video Input Modes
Multi-standard Output Format
Modes
V[7:0]
Active Video
Y
Cr Y FF 00 00 XY 80 10 80 10
EAV Code
4 Clocks
Figure 11. CCIR656 Input Mode Timing
Composite
Video
80 10 80 10 80 10
268 Clocks (NTSC)
280 Clocks (PAL)
Horizontal Blanking
Ancilliary Data
Output formats are configured by writing control
registers with the values shown in Table 3.
5.6.
The CS4954/5 automatically synthesizes NTSC
and PAL color subcarrier clocks using the CLK fre-
quency
(SC_SYNTH0/1/2/3). The NTSC subcarrier syn-
thesizer is reset every four fields (every eight fields
for PAL).
The SC_SYNTH0/1/2/3 registers used together
provide a 32-bit value that defaults to NTSC
(43E0F83Eh) following RESET. Table 4 shows the
32-bit value required for each of the different
broadcast formats.
5.7.
Since the subcarrier is synthesized from CLK the
subcarrier frequency error will track the clock fre-
quency error. If the input clock has a tolerance of
200 ppm then the resulting subcarrier will also
have a tolerance of 200 ppm. Per the NTSC speci-
fication, the final subcarrier tolerance is ±10 Hz
NTSC-M, NTSC-J
PAL-B, D, G, H, I, N 4.43361875 MHz 54131596
PAL-N (Argentina)
PAL-M
System
Subcarrier Generation
Subcarrier Compensation
80 10 80 10 FF 00 00 XY Cb Y Cr Cb Y Cr
and
3.5795455 MHz 43E0F83E
four
Table 3.
3.582056 MHz
3.579611 MHz
Fsubcarrier
SAV Code
4 Clocks
CS4954 CS4955
control
Active Video
Value (hex)
43CDDFC7
43ED288D
1440 Clocks
registers
21