CS4954-CQ Cirrus Logic Inc, CS4954-CQ Datasheet - Page 36

• Manufacturer Part Number: CS4954-CQ
• Description: Digital Video Encoder IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4954-CQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Ic Function: Digital Video Encoder IC
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Control Register 0
Address
Control Register 1
Address
36
Bit Number
Bit Name
Default
Bit Number
Bit Name
Default
Bit
7:5
Bit
7:6
4
3
2
1
0
5
4
3
2
1
0
Mnemonic
Mnemonic
CBCR_UV
CBCRSEL
IN_MODE
FLD_POL
LUM DEL
RGB_BW
CCIR656
TV_FMT
LPF ON
CH BW
PROG
MSTR
PED
0
0
7
0
7
0
×
×
00
01
LUM DEL
TV_FMT
selects the TV display format
000:
001:
010:
011:
100:
101:
110-111:
1 = Master Mode, 0 = Slave Mode
video input is in ITU R.BT656 format (0 = off, 1 = on)
Progressive scanning enable (enable = 1)
Input select (0 = solid background, 1 = use V [7:0] data)
enable YCbCr to YUV conversion (1 = enable, 0 = disable)
luma delay on the composite1 output
00:
01:
10:
11:
chroma lpf bandwidth (0 = 650 kHz, 1 = 1.3 Mhz)
chroma lpf on/off (0 = off, 1 = on)
0 = Full bandwidth on RGB, 1 = BW reduced to 2.5 MHz (3 dB point) (default 0)
Polarity of Field (0: odd field = 0,1: odd field = 1)
Pedestal offset (0: 0 IRE, 1: 7.5 IRE)
CbCr select (0 = chroma undelayed, 1 = chroma delayed by one clock)
CONTROL_0
CONTROL_1
6
0
6
0
CH BW
5
0
5
0
Read/Write
Read/Write
NTSC-M CCIR601 timing (default)
NTSC-M RS170A timing
PAL-B, D, G, H, I
PAL-M
PAL-N (Argentina)
PAL-N (non Argentina)
reserved
no delay (default)
1 pixel clock delay
2 pixel clock delay
3 pixel clock delay
LPF_ON
MSTR
4
0
4
0
Default Value = 01h
Default Value = 02h
CCIR656
RGB_BW
Function
Function
3
0
3
0
PROG
FLD
2
0
2
0
CS4954 CS4955
IN_MODE
PED
1
0
1
1
CBCR_UV
CBCRSEL
DS278PP4
0
1
0
0