CS4954-CQ Cirrus Logic Inc, CS4954-CQ Datasheet - Page 30

• Manufacturer Part Number: CS4954-CQ
• Description: Digital Video Encoder IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4954-CQ

• No. Of Pins: 48
• Peak Reflow Compatible (260 C): No
• Ic Function: Digital Video Encoder IC
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.
7.1.
All CS4954/5 analog timing and sequencing is de-
rived from 27 MHz clock input. The analog outputs
are controlled internally by the video timing genera-
tor in conjunction with master and slave timing. The
video output signals perform accordingly for NTSC
and PAL specifications.
Being that the CS4954/5 is almost entirely a digital
circuit, great care has been taken to guarantee ana-
log timing and slew rate performance as specified
in the NTSC and PAL analog specifications. Refer-
ence the Analog Parameters section of this data
sheet for exact performance parameters.
7.2.
The CS4954/5 can operate with or without the aid
of an external voltage reference. The CS4954/5 is
designed with an internal voltage reference genera-
tor that provides a VREFOUT signal at the VREF
pin. The internal voltage reference is utilized by not
making a connection to the VREF pin. The VREF
pin can also be connected to an external precision
1.232 volt reference, which then overrides the in-
ternal reference.
7.3.
All six of the CS4954/5 digital to analog converter
DACs are output current normalized with a com-
mon ISET device pin. The DAC output current per
bit is determined by the size of the resistor connect-
ed between ISET and electrical ground. Typically a
4 K , 1% metal film resistor should be used. The
ISET resistance can be changed by the user to ac-
commodate varying video output attenuation via
post filters and also to suit individual preferred per-
formance.
In conjunction with the ISET value, the user can
also independently vary the chroma, luma and col-
orburst amplitude levels via host addressable con-
trol register bits that are used to control internal
30
ANALOG
Analog Timing
VREF
ISET
digital amplifiers. The DAC output levels are de-
fined by the following operations:
CVBS/Y/C/R/G/B outputs in low impedance mode:
CVBS/Y/C/R/G/B outputs in high impedance mode:
7.4.
The CS4954/5 is equipped with six independent,
video-grade, current-output, digital-to-analog con-
verters (DACs). They are 10-bit DACs operating at
a 27 MHz two-times-oversampling rate. All six
DACs are disabled and default to a low power
mode upon RESET. Each DAC can be individually
powered down and disabled. The output-current-
per-bit of all six DACs is determined by the size of
the resistor connected between the ISET pin and
electrical ground.
7.4.1. Luminance DAC
The Y pin is driven from a 10-bit 27 MHz current
output DAC that internally receives the Y, or lumi-
nance portion, of the video signal (black and white
only). Y is designed to drive proper video levels
into a 37.5
section of this data sheet for the exact Y digital to
analog AC and DC performance data. A EN_L en-
able control bit in the Control Register 5 (0×05) is
provided to enable or disable the luminance DAC.
For a complete disable and lower power operation
the luminance DAC can be totally shut down via
the SVIDLUM_PD control bit in the Control Regis-
ter 4 (0×04). In this mode, turn-on through the con-
trol register will not be instantaneous.
7.4.2. Chrominance DAC
The C pin is driven from a 10-bit 27 MHz current
output DAC that internally receives the C or
VREF/RISET = IREF
(e.g., 1.232 V/4K
VOUT (max) = IREF*(16/145)*1023*37.5
VOUT (max) = IREF*(4/145)*1023*150 = 1.304 V
DACs
load. Reference the detailed electrical
= 308 A
CS4954 CS4955
DS278PP4
= 1.304V