IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 172
![IP CORE - X1 Lane PCI Express For Arria GX](/photos/24/19/241936/4696145_sml.jpg)
IP-AGX-PCIE/1
Manufacturer Part Number
IP-AGX-PCIE/1
Description
IP CORE - X1 Lane PCI Express For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/1
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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7–12
PCI Express Compiler User Guide
Refer to
Figure 7–9. Arria GX, Stratix II GX, or Stratix IV GX PHY ×1 and ×4 and Arria II GX ×1, ×4, and ×8
with 100 MHz Reference Clock
Note to
(1) Different device families require different frequency ranges for the calibration and reconfiguration clocks. To
100 MHz Reference Clock and 250 MHz Application Clock
When HardCopy IV GX, Stratix II GX PHY, Stratix IV GX, or Stratix V GX is used in a
×8 configuration, the 100 MHz clock is connected directly to the transceiver. The
clk250_out is driven by the output of the transceiver.
The clk250_out must be connected to the clk250_in input, possibly through a clock
distribution circuit needed in the specific application. The user application interface is
synchronous to the clk250_in input.
determine the frequency range for your device, refer to one of the following device handbooks:
Architecture
Handbook,
Stratix V devices.
Figure
Figure 7–9
Clock Source
Clock Source
Clock Source
Calibration
100-MHz
7–9:
Reconfig
Transceiver Architecture
in Volume II of the Arria II Device Handbook,
for this clocking configuration.
refclk
<variant>.v or .vhd
in Volume 2 of the Stratix IV Device Handbook, or
<variant>_serdes.v or .vhd
rx_cruclk
pll_inclk
cal_blk_clk
reconfig_clk
fixedclk
(PCIe MegaCore Function)
<variant>_core.v or .vhd
(ALTGX or ALT2GX
Megafunction)
Transceivers
tx_clk_out
in Volume 2 of the Cyclone IV Device
December 2010 Altera Corporation
clk62.5_out
clk125_out
Chapter 7: Reset and Clocks
Altera PHY IP User Guide
or
Transceiver
Application C
Clocks
for
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