IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 270
![IP CORE - X1 Lane PCI Express For Arria GX](/photos/24/19/241936/4696145_sml.jpg)
IP-AGX-PCIE/1
Manufacturer Part Number
IP-AGX-PCIE/1
Description
IP CORE - X1 Lane PCI Express For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/1
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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15–42
Table 15–36. shmem_display VHDL Procedure/ or Verilog Function
Table 15–37. shmem_fill Procedure
Table 15–38. shmem_chk_ok Function (Part 1 of 2)
PCI Express Compiler User Guide
Location
Syntax
Arguments addr
Location
Syntax
Arguments addr
Location
Syntax
altpcietb_bfm_shmem.v or altpcietb_bfm_shmem.vhd
shmem_fill(addr, mode, leng, init)
mode
leng
init
altpcietb_bfm_shmem.v or altpcietb_bfm_shmem.vhd
result:= shmem_chk_ok(addr, mode, leng, init, display_error)
altpcietb_bfm_shmem.v or altpcietb_bfm_shmem.vhd
VHDL: shmem_display(addr, leng, word_size, flag_addr, msg_type)
Verilog HDL: dummy_return:=shmem_display(addr, leng, word_size, flag_addr, msg_type);
leng
word_size
flag_addr
msg_type
shmem_display VHDL Procedure or Verilog HDL Function
The shmem_display VHDL procedure or Verilog HDL function displays a block of
data from the BFM shared memory.
shmem_fill Procedure
The shmem_fill procedure fills a block of BFM shared memory with a specified data
pattern.
shmem_chk_ok Function
The shmem_chk_ok function checks a block of BFM shared memory against a specified
data pattern.
BFM shared memory starting address for displaying data.
Length, in bytes, of data to display.
Size of the words to display. Groups individual bytes into words. Valid values are 1, 2, 4, and
8.
Adds a <== flag to the end of the display line containing this address. Useful for marking
specific data. Set to a value greater than 2**21 (size of BFM shared memory) to suppress the
flag.
Specifies the message type to be displayed at the beginning of each line. See
Message Procedures” on page 15–43
of the constants defined in
BFM shared memory starting address for filling data.
Data pattern used for filling the data. Should be one of the constants defined in section
“Shared Memory Constants” on page
Length, in bytes, of data to fill. If the length is not a multiple of the incrementing data pattern
width, then the last data pattern is truncated to fit.
Initial data value used for incrementing data pattern modes In VHDL. This argument is type
std_logic_vector(63 downto 0). In Verilog HDL, this argument is reg [63:0].
In both languages, the necessary least significant bits are used for the data patterns that are
smaller than 64 bits.
Table 15–39 on page
15–41.
for more information about message types. Set to one
15–44.
Chapter 15: Testbench and Design Example
December 2010 Altera Corporation
BFM Procedures and Functions
“BFM Log and
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