IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 350
![IP CORE - X1 Lane PCI Express For Arria GX](/photos/24/19/241936/4696145_sml.jpg)
IP-AGX-PCIE/1
Manufacturer Part Number
IP-AGX-PCIE/1
Description
IP CORE - X1 Lane PCI Express For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/1
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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C–8
PCI Express Compiler User Guide
Stratix II GX Devices
Stratix III Family
Table C–13
Stratix II and Stratix II GX (EP2SGX130GF1508C3) devices for a maximum payload of
256 bytes with different parameters, using the Quartus II software, version 10.1.
Table C–13. Performance and Resource Utilization, Descriptor/Data Interface - Stratix II and
Stratix II GX Devices
Table C–14
Stratix III (EP3SL200F1152C2) devices for a maximum payload of 256 bytes with
different parameters, using the Quartus II software, version 10.1.
Table C–14. Performance and Resource Utilization, Descriptor/Data Interface - Stratix III Family
Notes to
(1) C4 device used.
(2) C3 device used.
×1/ ×4
×1
×1
×1/ ×4
×1
×1
×4
×4
×8
×8
×1
×1
×4
×4
(1)
(2)
Table
Clock (MHz)
shows the typical expected performance and resource utilization of the
shows the typical expected performance and resource utilization of
Parameters
Internal
C–14:
Clock (MHz)
Parameters
125
125
125
125
250
250
Internal
62.5
62.5
125
125
125
125
Channels
Virtual
Channels
1
2
1
2
1
2
Virtual
1
2
1
2
1
2
Combinational
Combinational
ALUTs
5000
6200
6600
7600
6200
6900
ALUTs
5100
6200
5300
6200
6700
7700
Registers
Logic
3500
4400
4500
5300
5600
6200
Size
Dedicated
Registers
December 2010 Altera Corporation
Size
3800
4600
3900
4800
4500
5300
Descriptor/Data Interface
M512
Memory Blocks
10
1
2
5
6
8
M9K Memory
Blocks
12
8
7
3
7
9
Chapter :
M4K
13
13
21
16
16
9
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