IP-AGX-PCIE/1 Altera, IP-AGX-PCIE/1 Datasheet - Page 30
![IP CORE - X1 Lane PCI Express For Arria GX](/photos/24/19/241936/4696145_sml.jpg)
IP-AGX-PCIE/1
Manufacturer Part Number
IP-AGX-PCIE/1
Description
IP CORE - X1 Lane PCI Express For Arria GX
Manufacturer
Altera
Datasheet
1.IP-AGX-PCIE1.pdf
(362 pages)
Specifications of IP-AGX-PCIE/1
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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2–4
PCI Express Compiler User Guide
Table 2–2. PCI Registers (Part 2 of 2)
11. Click Next to display the Capabilities page.
Table 2–3. Capabilities Parameters
PCI Base Registers (Type 0 Configuration Space)
Vendor ID
Subsystem vendor ID
Class code
Tags supported
Implement completion timeout disable
Implement advanced error reporting
MSI messages requested
Link common clock
Data link layer active reporting
Surprise down reporting
Link port number
Enable slot capability
Slot capability register
Implement MSI-X
Pending Bit Array (PBA)
for the Capabilities parameters.
Completion timeout range
Implement ECRC check
Implement ECRC generation
Implement ECRC forwarding
MSI message 64–bit address capable
Table size
Offset
BAR indicator (BIR)
Offset
BAR Indicator
Parameter
Device Capabilities
0xFF0000
MSI-X Capabilities
Link Capabilities
0x1172
0x5BDE
Slot Capabilities
MSI Capabilities
Error Reporting
Table 2–3
32
Turn this option On
ABCD
Off
Off
Off
Off
4
On
On
Off
Off
0x01
Off
0x0000000
Off
0x000
0x00000000
0
0x00000000
0
provides the correct settings
December 2010 Altera Corporation
Parameterize the PCI Express
Chapter 2: Getting Started
Value
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