ATA6603-EK Atmel, ATA6603-EK Datasheet - Page 278
ATA6603-EK
Manufacturer Part Number
ATA6603-EK
Description
MCU, MPU & DSP Development Tools Demoboard LIN-MCM
Manufacturer
Atmel
Datasheet
1.ATA6603P-PLQW.pdf
(360 pages)
Specifications of ATA6603-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 278 of 360
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4.21.6.3
278
ATA6602/ATA6603
The ADC Data Register – ADCL and ADCH
ADLAR = 0
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
Initial Value
Initial Value
Read/Write
Read/Write
These bits represent the result from the conversion, as detailed in
on page
Bit
Bit
275.
ADC7
ADC9
ADC1
15
15
R
R
R
R
–
7
0
0
7
0
0
ADC6
ADC8
ADC0
14
14
R
R
R
R
–
6
0
0
6
0
0
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
0
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
ADC3
ADC5
11
11
R
R
R
R
–
3
0
0
–
3
0
0
ADC2
ADC4
10
10
R
R
R
R
–
2
0
0
–
2
0
0
ADC9
ADC1
ADC3
“ADC Conversion Result”
R
R
R
R
9
1
0
0
9
–
1
0
0
ADC8
ADC0
ADC2
R
R
R
R
8
0
0
0
8
–
0
0
0
4921E–AUTO–09/09
ADCH
ADCH
ADCL
ADCL
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