AT85C5122D-SISUM Atmel, AT85C5122D-SISUM Datasheet
AT85C5122D-SISUM
Specifications of AT85C5122D-SISUM
Related parts for AT85C5122D-SISUM
AT85C5122D-SISUM Summary of contents
Page 1
Features • Clock Controller – 80C51 core with 6 clocks per instruction – 8 MHz On-Chip Oscillator – PLL for generating clock to supply CPU core, USB and Smart Card Interfaces – Programmable CPU clock from 500 KHz / X1 ...
Page 2
Reference Documents AT8xC5122/23 2 The user must get the following additionnal documents which are not included but which complete this product datasheet • Product Errata Sheet • Bootloader Datasheet 4202E–SCR–06/06 ...
Page 3
Product Description 4202E–SCR–06/06 AT8xC5122/23 products are high-performance CMOS derivatives of the 80C51 8-bit microcontrollers designed for USB smart card reader applications. The AT8xC5122 is proposed in four versions : - ROM version with or without internal data E2PROM. The ROM ...
Page 4
Table 1. Product versions Features AT83C5122 VQFP64 QFN64 Packages PLCC28 Die Form Program memory 32KB ROM Internal Data E2PROM No Embedded bootloader No VQFP32, QFN32 packages Features PLCC68, VQFP64,QFN64 packages PLCC28 package AT8xC5122/23 4 AT83EC5122 AT85C5122 PLCC68 VQFP64 VQFP64 PLCC28 ...
Page 5
AT8xC5122 Block Diagram 3.3 V Regulator XTAL1 8 MHz 256 x 8 Oscillator RAM XTAL2 PLLF PLL WATCH-DOG POR RST PFD RESET 8-BIT 3-BIT 8-BIT PORT PORT PORT AT83C5123 Block Diagram 3.3 V Regulator XTAL1 8 MHz 256 x 8 ...
Page 6
Pinout High Pin Count Package Description AT8xC5122 version AT8xC5122/23 6 Figure 1. VQFP64 Package Pinout DVCC 2 P1.2/CPRES CC8 3 P5.7/KB7 4 5 P5.6/KB6 6 CRST P5.5/KB5 7 P5.4/KB4 8 CC4 9 ...
Page 7
Figure 2. PLCC68 Package Pinout (for engineering purpose only DVCC 10 P1.2/CPRES 11 CC8 12 P5.7/KB7 13 P5.6/KB6 14 CRST 15 P5.5/KB5 16 P5.4/KB4 17 CC4 18 P5.3/KB3 19 P5.2/KB2 20 CCLK 21 ...
Page 8
AT8xC5122/23 8 Figure 3. QFN64 Package Pinout DVCC 1 2 P1.2/CPRES CC8 3 P5.7/KB7 4 5 P5.6/KB6 CRST 6 P5.5/KB5 7 P5.4/KB4 8 CC4 9 10 P5.3/KB3 P5.2/KB2 11 CCLK 12 13 P5.1/KB1 ...
Page 9
AT89C5122DS version 4202E–SCR–06/06 Figure 4. VQFP64 Package Pinout DVCC 1 2 P1.2/CPRES CC8 3 P5.7/KB7 4 5 P5.6/KB6 CRST 6 P5.5/KB5 7 P5.4/KB4 8 CC4 9 10 P5.3/KB3 P5.2/KB2 11 CCLK 12 13 ...
Page 10
AT8xC5122/23 10 Figure 5. QFN64 Package Pinout DVCC 1 2 P1.2/CPRES CC8 3 P5.7/KB7 4 5 P5.6/KB6 CRST 6 P5.5/KB5 7 P5.4/KB4 8 CC4 9 10 P5.3/KB3 P5.2/KB2 11 CCLK 12 13 P5.1/KB1 ...
Page 11
Low Pin Count Package Description AT8xC5122 and AT83C5123 versions AT83C5123 version 4202E–SCR–06/06 Figure 6. PLCC28 Package Pinout DVCC 5 6 P1.2/CPRES 7 CC8 8 CRST 9 CC4 10 CCLK VSS 11 Figure 7. VQFP32 Package Pinout 32 1 DVCC 2 ...
Page 12
AT8xC5122/23 12 Figure 8. QFN32 Package Pinout 32 DVCC 1 P1.2/CPRES 2 CC8 3 CRST 4 CC4 5 6 CCLK P5 VSS P3.1/TxD 23 P1.6 22 P3.0/RxD 21 P3.5/T1/CRST1 ...
Page 13
Pin Description Table 2. Pin Description Port ...
Page 14
Table 2. Pin Description (Continued) Port ...
Page 15
Table 2. Pin Description (Continued) Port RST ...
Page 16
Table 2. Pin Description (Continued) Port PSEN PLLF AVCC VCC CVCC ...
Page 17
Typical Applications Recommended External components Table 3. External Components Bill Of Materials Reference Description R1 USB Full Speed Pull-up R2 USB pad serial resistor R3 USB pad serial resistor R4 PLL filter resistor R5 CIO Pull-up resistor C1 Power Supply ...
Page 18
USB Keyboard with Smart Card Reader Using the AT8xC5122 and AT89C5122DS Versions USB VCC VBUS D+ D- GND GND Keyboard Matrix R4 C3 Notes : 1 - Pin configuration depends on product versions AT8xC5122/23 18 VCC VCC C9 C8 GND ...
Page 19
USB Smart Card Reader Using the AT83C5123 Version VCC 10mA Max USB VCC VBUS D+ D- GND GND R4 C3 GND 4202E–SCR–06/06 VCC VCC C9 C8 GND GND VCC AVCC EA DVCC C4 GND R1 VREF ...
Page 20
Memory Organization Program Memory Managament AT8xC5122/23 20 The AT8xC5122/23 devices have separated address spaces for Program and Data Memory, as shown in Figure 13 on page 29, Figure 14 on page 31 and Figure 15 on page 32. The logical ...
Page 21
Data Memory Managament RAM Achitecture XRAM Achitecture 4202E–SCR–06/06 All device versions implements : - 256 Bytes of RAM to increase data parameter handling and high level language usage - 512 bytes of XRAM (Extended RAM) to store program data. The ...
Page 22
Dual Data Pointer Register (DDPTR) AT8xC5122/ access to external XRAM memory locations higher than the accessible size of the memory (roll-over feature) will be performed with the MOVX DPTR instructions, with P0 and P2 as data/address busses, WR ...
Page 23
Figure 11. Use of Dual Pointer 7 DPS AUXR1(A2H) Assembly Language 4202E–SCR–06/06 0 DPTR1 DPTR0 DPH(83H) DPL(82H) a. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3. ; Block move using dual ...
Page 24
Registers AT8xC5122/23 24 Table 5. Auxiliary Register - AUXR (8Eh DPU - - Bit Bit Number Mnemonic Description Disable weak Pull-up 7 DPU 0 1 Reserved 6-3 - The value read from this bit is indeterminate. Do ...
Page 25
Table 6. Auxiliary Register 1 AUXR1- (0A2h) for AT8xC5122 ENBOOT Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change these bits. Enable ...
Page 26
AT8xC5122’s CRAM and E2PROM Versions AT8xC5122/23 26 Table 8. CRAM Configuration Register - RCON (D1h Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do ...
Page 27
... Programming (ISP) mode which manages the transfer of the code in the volatile Pro- gram Memory (CRAM). For CRAM version, the code is supplied by the ATMEL’s FLexible In-system Program- ming software (FLIP) through USB or UART interface For E2PROM version, the code is supplied from the internal code E2PROM or by FLIP. ...
Page 28
Using CRAM Memory AT8xC5122/23 28 The CRAM is a read / write volatile memory that is mapped in the program memory space. Then when the power is switched off the code is lost and needs to be reload at each ...
Page 29
Figure 13. AT8xC5122’s CRAM and E2PROM Versions (E2PROM version) FFFF 32K INTERNAL Reset@ E2PROM (Read/Write) 8000 PROGRAM MEMORY DATA MEMORY (Read / Write) 4202E–SCR–06/ ENBOOT=0 ENBOOT=1 FFFF FFFF <F800> 32K INTERNAL EXTERNAL ROM PROGRAM MEMORY (Read Only) ...
Page 30
AT8xC5122’s ROM Version Security Level AT8xC5122/23 30 The AT8xC5122’s ROM version implements : - ROM mapped from 0000h to 7FFFh in which is embedded the user code. The ROM device is only factory programmable. - 512 bytes ...
Page 31
Figure 14. AT8xC5122’s ROM Version PROGRAM MEMORY (Read only) 7FFF 0000 DATA MEMORY (Read / Write) 01FF 0000 4202E–SCR–06/06 EA=1 EA=0 FFFF EXTERNAL 8000 Roll-Over INTERNAL EXTERNAL 32K ROM RESET@ <0000> PSEN EXTRAM=1 EXTRAM=0 FFFF EXTERNAL XRAM 0200 Roll-Over 01FF ...
Page 32
AT83C5123 Version Figure 15. AT83C5123’s Device PROGRAM MEMORY (Read only) RESET@ <0000> OPTIONAL DATA MEMORY (Read / Write) AT8xC5122/23 32 The AT83C5123 device is a low pin count version of the AT8xC5122. The ROM version implements : - 30 KB ...
Page 33
Special Function Registers (SFR’s) Introduction 4202E–SCR–06/06 The Special Function Registers (SFRs) of the AT8xC5122/23 can be ranked into the fol- lowing categories: • C51 Core Registers: ACC, B, DPH, DPL, PSW, SP • System Configuration Registers: PCON, CKRL, CKCON0, CKCON1, ...
Page 34
AT8xC5122 Version Bit addressable 0/8 1/9 UEPINT F8h 0000 0000 LEDCON0 B F0h 0000 0000 0000 0000 P5 E8h 1111 1111 LEDCON1 ACC E0h 0000 0000 XX00 0000 D8h RCON PSW D0h 0000 0000 XXXX 0XXX C8h SCICLK S 1 ...
Page 35
AT83C5123 Version Bit addressable 0/8 1/9 UEPINT F8h 0000 0000 LEDCON0 B F0h 0000 0000 0000 0000 P5 E8h XXXX XXX1 ACC E0h 0000 0000 D8h PSW D0h 0000 0000 C8h SCICLK S 1 0X10 1111 P4 C C0h R ...
Page 36
SFR’s Description Table 10. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer Data Pointer Low byte (LSB DPL 82h of DPTR) Data Pointer High byte DPH ...
Page 37
Table 13. Timers SFRs Mnemonic Add Name TH0 8Ch Timer/Counter 0 High byte TL0 8Ah Timer/Counter 0 Low byte TH1 8Dh Timer/Counter 1 High byte TL1 8Bh Timer/Counter 1 Low byte Timer/Counter 0 and 1 TCON 88h control Timer/Counter 0 ...
Page 38
Table 17. Interrupt SFRs Mnemonic Add Name Interrupt Priority Control IPH0 B7h High 0 Interrupt Priority Control IPL1 B2h Low 1 Interrupt Priority Control IPH1 B3h High 1 ISEL A1h Interrupt Enable Register Table 18. SCIB SFRs Mnemonic Add Name ...
Page 39
Table 18. SCIB SFRs Mnemonic Add Name Smart Card Frequency SCICLK C1h Prescaler Register Table 19. DC/DC SFRs Mnemonic Add Name DC/DC Converter Reload DCCKPS BFh Register Table 20. Keyboard SFRs Mnemonic Add Name (1) KBF 9Eh Keyboard Flag Register ...
Page 40
Table 22. USB SFRs Mnemonic Add Name USB Endpoint Interrupt UEPIEN C2h Enable UEPDATX CFh USB Endpoint X Fifo Data USB Byte Counter Low UBYCTX E2h (EPX) UFNUML BAh USB Frame Number Low UFNUMH BBh USB Frame Number High Table ...
Page 41
Clock Controller On-Chip Oscillator Quartz Specification 4202E–SCR–06/06 The clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All the internal clocks to the CPU core and peripherals are generated by this controller. The on-chip ...
Page 42
Phase Lock Loop (PLL) PLL Description CK_XTAL1 PLL Programming AT8xC5122/23 42 The AT8xC5122/23’s PLL is used to generate internal high frequency clock synchro- nized with an external low-frequency. Figure 17 shows the internal structure of the PLL. The PFLD block ...
Page 43
Clock Tree Architecture 4202E–SCR–06/06 Figure 19. PLL Programming Flow PLL Programming Configure Dividers xxxxb N3:0= xxxxb R3:0= Enable PLL PLLEN= 1 PLL Locked? PLOCK= 1? The clock controller outputs several different clocks as shown in Figure 20: • a clock ...
Page 44
Figure 20. Clock Tree Diagram CK_XTAL1 XTAL1 XTAL2 PD PCON.1 CPU and Peripheral Clocks AT8xC5122/23 44 PR4 DCCKPS[3:0] CK_XTAL1 0 PR1 CK_PLL 1 CKRL[3:0] CKS CKSEL.0 PLL CK_PLL 96 MHz PLLEN PLLCON.1 XTSCS SCICLK.7 EXT48 PLLCON.2 1/2 Two clocks sources ...
Page 45
X1 and X2 Modes 4202E–SCR–06/06 The CPU and peripherals clocks frequencies are defined in the table below. CKS Use of on-chip oscillator When the CPU and Peripherals clocks are fed by ...
Page 46
AT8xC5122/23 46 Figure 21. X1 mode PR1 prescaler Crystal 1/2 8 MHz When the X1 mode is selected, the CPU and Peripherals work at 8Mhz / X1 Figure 22. X2 mode Crystal 8 MHz Internal Prescaler 1/2 When the X2 ...
Page 47
Use of PLL Clock 4202E–SCR–06/06 PR1 Prescaler Crystal 8 MHz 1/8 External Clock X1 mode selected 1/2 2 MHz External Clock X2 mode selected 1 MHz When the CPU clock is fed by the PLL, the X2 mode is forbidden. ...
Page 48
SCIB Clock AT8xC5122/23 48 Prescaler PLL 1/4 96 MHz X1 mode selected External Clock 48 MHz 1/2 External Clock X2 mode selected 24 MHz The Smart Card Interface Block (SCIB) uses two clocks : – The first one, CK_IDLE, is ...
Page 49
Alternate Card Clock DC/DC Converter Clock 4202E–SCR–06/06 If the CK_CPU <= 4/3 * CK_ISO, the SCIB doesn’t work. If the CK_CPU >= 6* CK_ISO, the programmer must take care in three cases: • Read (or write) operation on a SCIB ...
Page 50
USB Interface Clock Registers AT8xC5122/23 50 The USB Interface uses two clocks : – The first one is the CPU clock used for the interface with the microcontroller, CK_IDLE. – The second one is the CK_USB supplied from the PLL ...
Page 51
Table 26. Clock Configuration Register 0 - CKCON0 (S:8Fh WDX2 - Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Watchdog clock This ...
Page 52
AT8xC5122/23 52 Table 27. Clock Configuration Register 1 - CKCON1 (S:AFh) only for AT8xC5122 Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not ...
Page 53
I/O Port Definition Ports vs Packages Port 0 4202E–SCR–06/06 Table 30. I/O Number vs Packages P0 P1 VQFP64 8 8 QFN64 VQFP32 - 8 QFN32 PLCC28 - 6 Port 0 has the following functions: – Default function: Port 0 is ...
Page 54
Port 1 Alternate Function Port Signal Description Smart card interface function CIO Card I/O Smart card interface function CC8 Card contact 8 Smart card interface function P1.2 CPRES Card presence Smart card interface function CC4 Card contact 4 Smart card ...
Page 55
Port 3 Alternate Functions Port Signal Description Receiver data input (asynchronous) or data input/output P3.0 RxD (synchronous) of the serial interface Transmitter data output (asynchronous) or clock output P3.1 TxD (synchronous) of the serial interface P3.2 INT0 External interrupt 0 ...
Page 56
Port 4 Port 5 AT8xC5122/23 56 Port 4 has the following functions: – Default function: Port 6-bit I/O port. – Alternate functions: see table below Port 4 has the following configurations: – Default configuration: Pseudo bi-directional “Port51” ...
Page 57
Port Configuration Standard I/O P0 Quasi Bi-directional Port 4202E–SCR–06/06 The P0 port is described in Figure 23. Figure 23. Standard Input/Output Port ADDR/DATA CONTROL Port latch Data Input Data The default port output configuration for standard I/O ports is the ...
Page 58
Push-pull Output Configuration Input with Medium or Weak Pull-up Configuration AT8xC5122/23 58 The “Port51” is described in Figure 24. Figure 24. Quasi Bi-directional Port 2 CPU CLOCK DELAY Port Latch Data Input Data The push-pull output configuration has the same ...
Page 59
Input with Weak Pull-down Configuration Low Speed Output Configuration LED Source Current 4202E–SCR–06/06 Figure 26. Input with Pull-up Stuck Medium Stuck Weak Input Data The input with pull-down (input WPD) configuration is shown in ...
Page 60
AT8xC5122/23 60 Figure 29. LED Source Current LEDx.0 Port Latch Data LEDx.1 Notes: 1. When switching a low level, LEDCTRL device has a permanent current of about N mA/ 8). 2. The port must be ...
Page 61
Registers 4202E–SCR–06/06 Table 36. Port Mode Register 0 - PMOD0 (91h) for AT8xC5122 P3C1 P3C0 P2C1 Bit Number Bit Mnemonic Description Port 3 Configuration bits (Applicable to P3.0, P3.1, P3.3, P3.4 only) 00 Quasi bi-directional 7 - ...
Page 62
AT8xC5122/23 62 Table 38. Port Mode Register 1 - PMOD1 (84h) for AT8xC5122 P5HC1 P5HC0 P5MC1 Bit Number Bit Mnemonic Description Port 5 High Configuration bits (Applicable from P5.6 to P5.7 only) 00 Quasi bi-directional 7 - ...
Page 63
Table 40. LED Port Control Register 0 - LEDCON0 (F1h LED3.1 LED3.0 LED2.1 Bit Number Bit Mnemonic Description Port LED3 Configuration bits 00 LED control disabled LED3 current source when ...
Page 64
Smart Card Interface Block (SCIB) AT8xC5122/23 64 The SCIB provides all signals to interface directly with a smart card. The compliance with the ISO7816, EMV’2000, GSM and WHQL standards has been certified. Both synchronous (e.g. memory card) and asynchronous smart ...
Page 65
Block Diagram Definitions Terminal and ICC ETU T=0 T=1 Activation: Cold Reset Activation: Warm Reset De-Activation 4202E–SCR–06/06 The Smart Card Interface Block diagram is shown Figure 30: Figure 30. SCIB Block Diagram Barrel shifter Clk_iso Clk_cpu Etu counter Guard time ...
Page 66
ATR F and D Guard Time Extra Guard Time Block Guard Time Work Waiting Time (WWT) Character Waiting Time (CWT) In T=1 protocol CWT is the interval between the leading edge of 2 consecutive charac- Block Waiting Time (BWT) Waiting ...
Page 67
Functional Description Barrel Shifter SCART FSM ETU Counter Guard Time Counter 4202E–SCR–06/06 IEC7816-3 says this procedure is mandatory in ATR for card supporting T=0 while EMV says this procedure is mandatory for T=0 but does not apply for ATR. The ...
Page 68
Block Guard Time Counter AT8xC5122/23 68 The Guard Time counter bit counter It is initialized at 001h at the start of a trans- mission by the Terminal. It then increments itself at each ETU until it reach ...
Page 69
ETU Counter Enable transmit Waiting Time (WT) Counter 4202E–SCR–06/06 Figure 32. Block Guard Time. RECEPTION from ICC CHAR 2 CHAR n CHAR 1 >= Block Guard Time Write “Block Guard Time” in SCGT1,0 and set BGTEN to transfer the value ...
Page 70
Figure 34. Waiting Time Counter ETU Counter WTEN Write_SCWT2 UART Start Bit AT8xC5122/23 70 When the WT counter times out, an interrupt is generated and the SCIB function is locked: reception and emission are disabled. It can be enabled by ...
Page 71
Figure 35. T=0 mode > GT CHAR 2 CHAR 1 < T=1 protocol : The maximum interval between the leading edge of the start bit of 2 consecutive characters sent by the ICC is called maximum Character ...
Page 72
Power-on and Power-off FSM AT8xC5122/23 72 The Power-on Power-off Finite State Machine (FSM) applies the signals on the smart card in accordance with ISO7816-3 standard. It conducts the Activation (Cold Reset and Warm Reset as well as De-Activation) it also ...
Page 73
Interrupt Generator 4202E–SCR–06/06 Removal of the smart card will automatically start the power off sequence as described in Figure 39. The SCIB deactivation sequence after a reset of the CPU or after a lost of power supply is ISO7816-3 compliant. ...
Page 74
Additional Features Clock XTAL1 (MHz) EXT48 Card Presence Input AT8xC5122/23 74 The CK_ISO input must be in the range MHz according to ISO 7816. The CK_ISO can be programmed up to ...
Page 75
Transmit / Receive Buffer 4202E–SCR–06/06 The contents of the SCIBUF Transmit / Receive Buffer is transferred or received into / from the Shift Register. The Shift Register is not accessible by microcontroller. Its role is to prepare the byte to ...
Page 76
Transmitted Character AT8xC5122/23 76 Figure 43. CharacterTransmission Diagram SCISR register SCTBE SCIBUF SCTBI SCIIR register SCTC Shift Register I/O pin ESCTBI ESCTI SCTI SCPE Parity error Parity error SCPI 4202E–SCR–06/06 ...
Page 77
SCIB Reset Register Name SCICR SCCON SCISR SCIIR SCIER SCSR SCIBUF SCETU1, SCETU0 SCGT1, SCGT0 SCWT3, SCWT2, SCWT1, SCWT0 SCICLK 4202E–SCR–06/06 Figure 44. Character Reception Diagram SCISR register SCTBE Shift Register I/O pin SCTBI SCIIR register The SCICR register contains ...
Page 78
Alternate Card Registers AT8xC5122/ second card named ‘Alternate Card’ can be controlled. The Clock signal CCLK1 can be adapted to the XTAL frequency. Thanks to the clock prescaler which can divide the frequency ...
Page 79
Table 44. Smart Card Interface Control Register - SCICR (S:B6h, SCRS = RESET CARDDET Bit Number Bit Mnemonic Description Reset Set this bit to reset and deactivate the Smart Card Interface. 7 RESET Clear this bit to ...
Page 80
Table 45. Smart Card Contacts Register - SCCON (S:ACh, SCRS= CLK - Bit Number Bit Mnemonic 7 CLK CARDC8 4 CARDC4 3 CARDIO 2 CARDCLK 1 CARDRST 0 CARDVCC Reset Value = 0X00 0000b AT8xC5122/23 ...
Page 81
Table 46. Smart Card UART Interface Status Register - SCISR (S:ADh, SCRS= SCTBE CARDIN Bit Number Bit Mnemonic Description UART Transmit Buffer Empty Status This bit is set by hardware when the Transmit Buffer is copied to the ...
Page 82
Table 47. Smart Card UART Interrupt Identification Register (Read Only) SCIIR (S:AEh, SCRS= SCTBI - ICARDERR Bit Number Bit Mnemonic 7 SCTBI ICARDERR 4 VCARDERR 3 SCWTI 2 SCTI 1 SCRI 0 SCPI Reset Value ...
Page 83
Table 48. Smart Card UART Interrupt Enabling Register - SCIER (S:AEh, SCRS= ESCTBI - ICARDER Bit Number Bit Mnemonic 7 ESCTBI ICARDER 4 EVCARDER 3 ESCWTI 2 ESCTI 1 ESCRI 0 ESCPI Reset Value = ...
Page 84
Table 49. Smart Card Selection Register - SCSR (S:ABh BGTEN Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not change this bit. Block Guard Time Enable Set this ...
Page 85
Table 51. Smart Card ETU Register 1 - SCETU1 (S:ADh, SCRS= COMP - Bit Number Bit Mnemonic Description Compensation Clear this bit when no time compensation is needed (i.e. when the ETU to Card CLK period ratio is ...
Page 86
Table 53. Smart Card Transmit Guard Time Register 0 - SCGT0 (S:B4h, SCRS= GT7 GT6 Bit Number Bit Mnemonic Description Transmit Guard Time LSB The minimum time between two consecutive start bits in transmit mode is GT[8:0] * ...
Page 87
Table 56. Smart Card Character/Block Waiting Time Register 2 SCWT2 (S:B6h, SCRS= WT23 WT22 Bit Number Bit Mnemonic Description Waiting Time Byte2 WT[23:16] Used together with WT[31:24] and WT[15:0] in registers SCWT3,SCWT1, SCWT0 (see Table ...
Page 88
Table 59. Smart Card Clock Reload Register - SCICLK (S:C1h, SCRS= XTSCS - Bit Number Bit Mnemonic 7 XTSCS SCICLK[5:0] Reset Value = 0X10 1111b (default value for a divider by two) DC/DC ...
Page 89
Initialization Procedure Procedure for CVcc =< 3 volts 4202E–SCR–06/06 mode by 20% by means of bit OVFADJ in DCCKPS register. When the current overflow controller is operating, the ICARDOVF is set by the hardware in SCISR register. The current drawn ...
Page 90
AT8xC5122/23 90 Figure 46. Card Vcc = 1.8V Initialization Procedure SCICR.7=Reset=1 SCICR.7=Reset=0 VCARD[1: Mode Regulation DCCKPS[7]=1 BOOST[1:0]=01 SCCON CardVcc=1 Set Timeout VCARDOK=1 DC/DC Initialization DC/DC Initialization successful Timeout Expired Failure 4202E–SCR–06/06 ...
Page 91
Figure 47. Card Vcc = 3V Initialization Procedure SCICR.7=Reset=1 SCICR.7=Reset=0 VCARD[1: Mode Regulation DCCKPS[7]=1 BOOST[1:0]=01 SCCON CardVcc=1 Set Timeout VCARDOK=1 DC/DC Initialization AT8xC5122/23 DC/DC Initialization successful Timeout Expired Failure 91 ...
Page 92
Procedure for CVcc = 5volts AT8xC5122/23 92 The DC/DC pump mode must be selected (MODE = 0 in DCCKPS register). The detailed procedure is described in flow chart of Figure 48. Figure 48. Card Vcc = 5V Initialization Procedure SCICR.7=Reset=1 ...
Page 93
Monitoring Procedure Table 60. DC/DC converter status VCARDOK ICARDOVF 4202E–SCR–06/06 advised to decrement the BOOST[1:0] bits to restore the overflow current to its normal or desired value. Once the DC/DC has been successfuly initialized ...
Page 94
DC/DC Converter register Table 61. DC/DC Converter Control Register - DCCKPS (S:BFh MODE OVFADJ Bit Number Bit Mnemonic 7 MODE 6 OVFADJ BOOST[1: DCCKPS[3:0] Reset Value = 0000 0000b AT8xC5122/ ...
Page 95
USB Controller USB Mass Storage Classes USB Mass Storage Class CBI Transport USB Mass Storage Class Bulk- Only Transport USB Device Firmware Upgrade (DFU) 4202E–SCR–06/06 The AT8xC5122D implements a USB device controller supporting Full Speed data transfer. In addition to ...
Page 96
Description D+ D- Serial Interface Engine (SIE) AT8xC5122/23 96 The only possible value for the wMaxPacketSize in the DFU configuration is 32 bytes, which is the size of the FIFO implemented for endpoint 0. The USB device controller provides the ...
Page 97
Function Interface Unit (UFI) DPLL 4202E–SCR–06/06 Figure 50. SIE Block Diagram End of Packet Detection Start of Packet Detection D+ D- Clock Recovery Clk48 (48 MHz) The Function Interface Unit provides the interface between the AT8xC5122D (or AT83C5123) and the ...
Page 98
OUT Transactions: OUT DATA0 (n Bytes) HOST UFI C51 IN Transactions: IN HOST UFI C51 AT8xC5122/23 98 Figure 52. Minimum Intervention from the USB Device Firmware OUT ACK interrupt C51 Endpoint FIFO read (n bytes) IN DATA1 NACK Endpoint FIFO ...
Page 99
Configuration General Configuration Endpoint Configuration UEPSTA0 Endpoint 0 UEPSTA6 Endpoint 6 4202E–SCR–06/06 • USB controller enable Before any USB transaction, the 48 MHz required by the USB controller must be cor- rectly generated (Section "Clock Controller", page 41). The USB ...
Page 100
AT8xC5122/23 100 • Endpoint enable Before using an endpoint, this one should be enabled by setting the EPEN bit in the UEPCONX register. An endpoint which is not enabled won’t answer to any USB request. The Default Control Endpoint (Endpoint ...
Page 101
Endpoint FIFO reset Before using an endpoint, its FIFO should be reset. This action resets the FIFO pointer to its original value, resets the byte counter of the endpoint (UBYCTX register), and resets the data toggle bit (DTGL ...
Page 102
Read/Write Data FIFO Read Data FIFO Write Data FIFO AT8xC5122/23 102 The read access for each OUT endpoint is performed using the UEPDATX register. After a new valid packet has been received on an Endpoint, the data are stored into ...
Page 103
Bulk / Interrupt Transactions Bulk/Interrupt OUT Transactions in Standard Mode 4202E–SCR–06/06 Bulk and Interrupt transactions are managed in the same way. Figure 55. Bulk/Interrupt OUT transactions in Standard Mode HOST OUT DATA0 (n bytes) OUT DATA1 OUT DATA1 OUT DATA1 ...
Page 104
Bulk/Interrupt OUT Transactions in Ping-Pong Mode (Endpoints 6) AT8xC5122/23 104 Figure 56. Bulk / Interrupt OUT Transactions in Ping-Pong Mode HOST OUT DATA0 (n bytes) DATA1 (m bytes) OUT OUT DATA0 (p bytes) An endpoint should be first enabled and ...
Page 105
Bulk/Interrupt IN Transactions In Standard Mode 4202E–SCR–06/06 If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is ...
Page 106
Bulk/Interrupt IN Transactions in Ping-Pong Mode AT8xC5122/23 106 Figure 58. Bulk / Interrupt IN transactions in Ping-Pong mode HOST UFI IN NACK IN DATA0 (n Bytes) ACK IN DATA1 (m Bytes) ACK IN DATA0 (p Bytes) ACK An endpoint will ...
Page 107
Control Transactions Setup Stage Data Stage: Control Endpoint Direction Status Stage 4202E–SCR–06/06 The DIR bit in the UEPSTAX register should Receiving Setup packets is the same as receiving Bulk Out packets, except that the Rxsetup bit in ...
Page 108
Isochronous Transactions Isochronous OUT Transactions in Standard Mode Isochronous OUT Transactions in Ping-pong Mode AT8xC5122/23 108 An endpoint should be first enabled and configured before being able to receive Isochro- nous packets. When an OUT packet is received on an ...
Page 109
Isochronous IN Transactions in Standard Mode Isochronous IN Transactions in Ping-Pong Mode 4202E–SCR–06/06 If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet ...
Page 110
Miscellaneous USB Reset STALL Handshake Start of Frame Detection Frame Number Data Toggle Bit NAK Handshakes AT8xC5122/23 110 The EORINT bit in the USBINT register is set by hardware when a End of Reset has been detected on the USB ...
Page 111
Suspend/Resume Management Suspend Resume 4202E–SCR–06/06 The Suspend state can be detected by the USB controller if all the clocks are enabled and if the USB controller is enabled. The bit SPINT is set by hardware when an idle state is ...
Page 112
Detection of a SUSPEND State Detection of a RESUME State Note : WUPCPU bit must be Cleared before enabling the PLL Upstream Resume AT8xC5122/23 112 Figure 59. Example of a Suspend/Resume Management SPINT microcontroller in power-down WUPCPU A USB device ...
Page 113
SET_FEATURE: DEVICE_REMOTE_WAKEUP Detection of a SUSPEND state 4202E–SCR–06/06 Figure 60. Example of REMOTE WAKEUP Management SPINT UPRSM = 1 UPRSM upstream RESUME sent AT8xC5122/23 USB Controller Init Set RMWUPE Suspend management Need USB Resume Enable Clocks Clear SPINT Set SDMWUP ...
Page 114
Detach Simulation AT8xC5122/23 114 In order to be re-enumerated by the Host, the AT8xC5122/23 has the possibility to sim- ulate a DETACH-ATTACH of the USB bus. The V output voltage is between 3.0V and 3.6V. This output can be connected ...
Page 115
USB Interrupt System Interrupt System Priorities Figure 63. USB Interrupt Control System D+ USB Controller D- Interrupt Control System 4202E–SCR–06/06 EUSB EA IEN1.6 IEN0.7 Interrupt Enable Table 63. Priority Levels IPHUSB IPLUSB shown in Figure ...
Page 116
Figure 64. USB Interrupt Control Block Diagram Endpoint 0..6) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 UEPSTAX.6 RXSETUP UEPSTAX.2 STLCRC UEPSTAX.3 NAKOUT UEPCONX.5 NAKIN UEPCONX.4 NAKIEN UEPCONX.6 WUPCPU USBINT.5 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 ...
Page 117
Registers 4202E–SCR–06/06 Table 64. USB Global Control Register - USBCON (S:BCh USBE SUSPCLK SDRMWUP Bit Bit Number Mnemonic Description USB Enable Set this bit to enable the USB controller. 7 USBE Clear this bit to disable and ...
Page 118
AT8xC5122/23 118 Table 65. USB Global Interrupt Register - USBINT (S:BDh WUPCPU Bit Bit Number Mnemonic Description Reserved The value read from these bits is always 0. Do not change these ...
Page 119
Table 66. USB Global Interrupt Enable Register - USBIEN (S:BEh EWUPCPU Bit Bit Number Mnemonic Description Reserved The value read from these bits is always 0. Do not change these ...
Page 120
Table 68. USB Endpoint Number - UEPNUM (S:C7h Bit Number Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not change these bits. Endpoint Number Set this ...
Page 121
Table 70. USB Endpoint Status and Control Register X - UEPSTAX (S:CEh) X=EPNUM set in UEPNUM Register DIR RXOUTB1 Bit Bit Number Mnemonic Description Control Endpoint Direction This bit is used only if the endpoint is configured in ...
Page 122
AT8xC5122/23 122 Table 71. USB FIFO Data Endpoint X (X=EPNUM set in UEPNUM Register) - UEPDATX (S:CFh FDAT7 FDAT6 FDAT5 Bit Bit Number Mnemonic Description Endpoint X FIFO data FDAT [7:0] Data byte to ...
Page 123
Table 73. USB Endpoint FIFO Reset Register - UEPRST (S:D5h EP6RST EP5RST Bit Bit Number Mnemonic Description Reserved 7 - The value read from these bits is always 0. Do not change this bit. Endpoint ...
Page 124
AT8xC5122/23 124 Table 74. USB Endpoint Interrupt Register - UEPINT (S:F8h read-only EP6INT EP5INT Bit Bit Number Mnemonic Description Reserved 7 - The value read from these bits is always 0. Do not change this bit. ...
Page 125
Table 75. USB Endpoint Interrupt Enable Register - UEPIEN (S:C2h EP6INTE EP5INTE Bit Number Bit Mnemonic Description Reserved 7 - The value read from these bits is always 0. Do not change this bit. Endpoint ...
Page 126
Serial I/O Port Framing Error Detection AT8xC5122/23 126 The serial I/O port in the AT8xC5122/23 is compatible with the serial I/O port in the 80C52. The I/O port provides both synchronous and asynchronous communication modes. It operates as an Universal ...
Page 127
Automatic Address Recognition Given Address 4202E–SCR–06/06 Figure 67. UART Timings in Modes 2 and 3 RXD D0 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 The automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled ...
Page 128
Broadcast Address Reset Addresses Timer 1 AT8xC5122/23 128 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t care bit; for slaves B and C, bit 0 ...
Page 129
CK_ T1 T1 INT1# GATE1 TMOD.7 Internal Baud Rate Generator CK_ SI Synchronous Mode (Mode 0) 4202E–SCR–06/06 Figure 68. Timer 1 Baud Rate Generator Block Diagram / C/T1# TMOD.6 TR1 TCON.6 When using the Internal Baud Rate ...
Page 130
Transmission (Mode 0) Reception (Mode 0) AT8xC5122/23 130 Figure 70. Serial I/O Port Block Diagram (Mode 0) SCON.6 SCON.7 SM1 SM0 Mode Decoder Mode Controller CK_ TI RI SCON.1 SCON.0 IBRG CLOCK To start a transmission ...
Page 131
Baud Rate Selection (Mode 0) Asynchronous Modes (Modes 1, 2 and 3) T1 CLOCK IBRG CLOCK CK_ SI Mode 1 4202E–SCR–06/06 In mode 0, baud rate can be either fixed or variable. As shown in Figure 73, the selection is ...
Page 132
Modes 2 and 3 Modes 2 and 3 Transmission (Modes 1, 2 and 3) Reception (Modes 1, 2 and 3) Framing Error Detection (Modes 1, 2 and 3) AT8xC5122/23 132 Figure 76. Data Frame Format (Mode 1) Mode 1 D0 ...
Page 133
Baud Rate Selection (Modes 1 and 3) T1 CLOCK IBRG CLOCK BDRCON.2 4202E–SCR–06/06 In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud Rate Generator and allows different baud rate in ...
Page 134
Table 76. Internal Baud Rate Generator Value MHz CK_IDLE Baud Rate SPD SMOD1 BRL 115200 1 1 57600 1 1 38400 1 1 19200 1 1 9600 1 1 4800 MHz CK_IDLE ...
Page 135
Registers 4202E–SCR–06/06 Table 77. Serial Control Register - SCON (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. FE Set ...
Page 136
AT8xC5122/23 136 Table 78. Slave Address Mask Register for UART - SADEN (B9h Reset Value = 0000 0000b Table 79. Slave Address Register for UART - SADDR (A9h Reset Value = 0000 0000b Table ...
Page 137
Serial Port Interface (SPI) Features Signal Description Master Output Slave Input (MOSI) Master Input Slave Output (MISO) SPI Serial Clock (SCK) 4202E–SCR–06/06 Only for AT8xC5122. The Serial Peripheral Interface module (SPI) which allows full-duplex, synchronous, serial communication between the MCU ...
Page 138
Slave Select (SS) Baud Rate AT8xC5122/23 138 Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. Only one Master (SS high level) can drive the network. The ...
Page 139
Functional Description Operating Modes 4202E–SCR–06/06 Figure 84 shows a detailed structure of the SPI module. Figure 84. SPI Module Block Diagram IntClk /4 Clock /8 /16 Divider /32 /64 /128 Clock Select SPR2 SPEN SSDIS SPI Interrupt Request The Serial ...
Page 140
Master Mode Slave Mode Transmission Formats AT8xC5122/23 140 Figure 85. Full-duplex Master-Slave Interconnection MISO 8-bit Shift Register MOSI SPI SCK Clock Generator SS Master MCU The SPI operates in Master mode when the Master bit, MSTR is set. Only one ...
Page 141
SCK Cycle Number SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point SCK Cycle Number SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) ...
Page 142
Error Conditions Mode Fault (MODF) Write Collision (WCOL) Overrun Condition SS Error Flag ( SSERR ) Interrupts AT8xC5122/23 142 sions (Figure 88). This format may be preferable in systems having only one Master and only one Slave driving the MISO ...
Page 143
Registers Serial Peripheral Control Register (SPCON) 4202E–SCR–06/06 Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. ...
Page 144
AT8xC5122/23 144 Table 85. Serial Peripheral Control Register - SPCON (C3h SPR2 SPEN SSDIS Bit Bit R/W Number Mnemonic Mode Description Serial Peripheral Rate 2 7 SPR2 RW Bit with SPR1 and SPR0 define the clock rate ...
Page 145
Serial Peripheral Status Register (SPSTA) 4202E–SCR–06/06 Serial Peripheral Status Register contains flags to signal the following The conditions: • Data transfer complete • Write collision • Inconsistent logic level on SS pin (mode fault error) Table 86. Serial Peripheral Status ...
Page 146
Serial Peripheral DATa Register (SPDAT) AT8xC5122/23 146 The Serial Peripheral Data Register (Table 87 read/write buffer for the receive data register. A write to SPDAT places data directly into the shift register. No transmit buffer is available in ...
Page 147
Timers/Counters Timer/Counter Operations Timer 0 4202E–SCR–06/06 The AT8xC5122D implements two general-purpose, 16-bit Timers/Counters. Although they are identified as Timer 0, Timer 1, you can independently configure each to operate in a variety of modes as a Timer ...
Page 148
Mode 0 (13-bit Timer) FCK_Tx Tx INTx# GATEx TMOD reg Mode 1 (16-bit Timer) AT8xC5122/23 148 For normal Timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by the selected input. Setting GATE0 and TR0 allows external pin ...
Page 149
FCK_Tx Tx INTx# GATEx TMOD reg Mode 2 (8-bit Timer with Auto- Reload) FCK_Tx Tx INTx# GATEx TMOD reg 4202E–SCR–06/06 Figure 92. Timer/Counter Mode C/Tx# TMOD reg TRx TCON ...
Page 150
Mode 3 (Two 8-bit Timers) FCK_T0 /6 T0 INT0# GATE0 TMOD.3 FCK_T0 Timer 1 AT8xC5122/23 150 Mode 3 configures Timer 0 so that registers TL0 and TH0 operate as 8-bit Timers (see Figure 96). This mode is provided for applications ...
Page 151
Mode 0 (13-bit Timer) Mode 1 (16-bit Timer) Mode 2 (8-bit Timer with Auto- Reload) Mode 3 (Halt) 4202E–SCR–06/06 • When Timer mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1). For ...
Page 152
Registers AT8xC5122/23 152 Timer/Counter Control Register Table 88. TCON (S:88h TF1 TR1 TF0 Bit Bit Number Mnemonic Description Timer 1 Overflow flag 7 TF1 Cleared by the hardware when processor vectors interrupt routine. Set by the hardware ...
Page 153
Table 89. Timer/Counter Mode Control Register - TMOD (S:89h GATE1 C/T1# Bit Number Bit Mnemonic Description Timer 1 Gating Control bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 ...
Page 154
AT8xC5122/23 154 Table 90. Timer 0 High Byte Register - TH0 (S:8Ch Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 0 Reset Value = 0000 0000b Table 91. Timer 0 Low Byte Register - TL0 ...
Page 155
Keyboard Interface Introduction Description Interrupt 4202E–SCR–06/06 Only for AT8xC5122. The AT8xC5122/23 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low ...
Page 156
Power Reduction Mode Registers AT8xC5122/23 156 P5 inputs allow exit from idle and power-down modes as detailed in Section "Power- Down Mode". Table 94. Keyboard Flag Register - KBF (9Eh KBF7 KBF6 KBF5 Bit Bit Number Mnemonic ...
Page 157
Table 95. Keyboard Input Enable Register - KBE (9Dh KBE7 KBE6 KBE5 Bit Bit Number Mnemonic Description Keyboard line 7 Enable bit 7 KBE7 Cleared to enable standard I/O pin. Set to enable KBF.7 bit in ...
Page 158
AT8xC5122/23 158 Table 96. Keyboard Level Selector Register - KBLS (9Ch KBLS7 KBLS6 KBLS5 Bit Bit Number Mnemonic Description Keyboard line 7 Level Selection bit 7 KBLS7 Cleared to enable a low level detection on Port line ...
Page 159
Interrupt System Introduction Interrupt System Description 4202E–SCR–06/06 The AT8xC5122/23 implements an interrupt controller with 15 inputs but only 9 are used for : – two external interrupts (INT0 and INT1) – two timer interrupts (timers 0, 1), – the UART ...
Page 160
Figure 100. Interrupt Control System INT0# RXD RXEN ISEL.0 1 INT1 0 OELEV OEEN ISEL.3 ISEL.2 0 CPRES 1 CPLEV PRESEN ISEL.7 ISEL.1 RXD SERIAL INTERFACE CONTROLLER TXD 0 P5.x 1 KBLSx MISO SPI MOSI CONTROLLER SCK SMART CARD CIO ...
Page 161
INT1 Interrupt Vector INT1 Input RXD Input CPRES Input 4202E–SCR–06/06 The INT1 interrupt is multiplexed with the following three inputs: • INT1 : Standard 8051 interrupt input • RXD : Received data on UART • CPRES: Insertion or remove of ...
Page 162
Registers AT8xC5122/23 162 Table 98. Interrupt Enable Register 0 - IEN0 (A8h Bit Bit Number Mnemonic Description Enable All interrupt bit 7 EA Cleared to disable all interrupts. Set to enable all interrupts. Reserved ...
Page 163
Table 99. Interrupt Enable Register 1 - IEN1 (B1h) for AT8xC5122 EUSB - Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not change this bit. USB ...
Page 164
AT8xC5122/23 164 Table 100. Interrupt Enable Register 1 - IEN1 (B1h) for AT83C5123 EUSB - Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not change this bit. ...
Page 165
Table 102. Interrupt Priority High Register 0 - IPH0 (B7h Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change these bits. ...
Page 166
AT8xC5122/23 166 Table 103. Interrupt Priority Low Register 1 - IPL1 (B2h) for AT8xC5122 PUSBL - Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not change this ...
Page 167
Table 104. Interrupt Priority Low Register 1 - IPL1 (B2h) for AT83C5123 PUSBL - Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not change this bit. ...
Page 168
AT8xC5122/23 168 Table 105. Interrupt Priority High Register 1 - IPH1 (B3h) for AT8xC5122 PUSBH - Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not change this bit. ...
Page 169
Table 106. Interrupt Priority High Register 1 - IPH1 (B3h) for AT83C5123 PUSBH - Bit Bit Number Mnemonic Reserved 7 - The value read from this bit is indeterminate. Do not change this bit. USB ...
Page 170
AT8xC5122/23 170 Table 107. Interrupt Enable Register - ISEL (S:A1h CPLEV - PRESIT Bit Bit Number Mnemonic Description Card presence detection level This bit indicates which CPRES level will bring about an interrupt Set this bit to ...
Page 171
Interrupt Sources and Vectors 4202E–SCR–06/06 Table 108. Interrupt Vectors Interrupt Source Reset INT0 Timer 0 INT1 Timer 1 UART Reserved Reserved (1) Keyboard Controller Reserved (1) SPI Controller Smart Card Controller Reserved Reserved USB Controller Reserved Note: 1. Only fot ...
Page 172
Microcontroller Reset Introduction AT8xC5122/23 172 The internal reset is used to start up (cold reset re-start (warm reset) the micro- controller activity. When the reset is applied (active state), all internal registers are initialized so that the microcontroller ...
Page 173
Power On Reset (POR) Power Fail Detector (PFD) 4202E–SCR–06/06 The role of the POR is to monitor the power supply rise of the microcontroller core and release the internal reset only when the internal voltage exceeds the VPFDP threshold from ...
Page 174
VCore VPFDP VPFDM Internal Reset 1 0 VCore VPFDP VPFDM Internal Reset 1 0 AT8xC5122/23 174 Figure 102. Static behaviour of POR and PFD Figure 103. Dynamic behaviour of POR and PFD t<50ns t t>50ns t 4202E–SCR–06/06 ...
Page 175
Reset pin Long Reset Reset Controlled by the User 4202E–SCR–06/06 As explained in the POR section there is no need to use the reset pin as the internal reset function at power up is ensured by the POR. Anyway, if ...
Page 176
Reset Controlled by an External Superviser Device AT8xC5122/23 176 As the reset pin can be forced in output by the Watch-Dog timer (WDT) or the POR/PFD features, there can be a conflict between the external superviser device and the micro- ...
Page 177
Watchdog Timer RESET 4202E–SCR–06/06 The AT8xC5122/23 microcontrollers contain a powerfull programmable hardware Watchdog Timer (WDT) that automatically resets the chip if its software fails to reset the WDT before the selected time interval has elapsed. It permits large timeout ranking ...
Page 178
AT8xC5122/23 178 Table 109. Watchdog Timer Out Register - WDTPRG (0A7h Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not change these bits. ...
Page 179
Table 111. Timeout value for F CK_WD Table 112. Watchdog Timer Enable register (Write Only) - WDTRST (A6h ...
Page 180
Power Management Idle Mode Power Down Mode AT8xC5122/23 180 Before activating the Idle Mode or Power Down Mode, the CPU clock must be switched to on-chip oscillator source if the PLL is used to fed the CPU clock. An instruction ...
Page 181
INT0 INT1 XTAL1 Table State of Ports Mode Program Memory ALE Idle Internal 1 Idle External 1 Power-down Internal 0 Power-down External 0 Note: 1. Port 0 can force a 0 level. A "one" will leave port floating. Reduced EMI ...
Page 182
USB Interface Suspend Resume AT8xC5122/23 182 The Suspend state can be detected by the USB controller if all the clocks are enabled and if the USB controller is enabled. The bit SPINT is set by hardware when an idle state ...
Page 183
Detection of a SUSPEND State Detection of a RESUME State Note : WUPCPU bit must be Cleared before enabling the PLL Smart Card Interface Entering in Power-down Mode In order to reduce the power consumption, a power-down or idle mode ...
Page 184
Keyboard Interface Entering in Power-down Mode In order to reduce the power consumption, the microcontroller can be set in power-down Exiting from Power-down Mode Watchdog Timer during Power-down and Idle Mode AT8xC5122/23 184 The keyboard interface applies only to AT8xC5122 ...
Page 185
Registers 4202E–SCR–06/06 Table 113. Power Control Register - PCON (S:87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 for UART 7 SMOD1 Set to select double baud rate in mode 1,2 or ...
Page 186
Electrical Characteristics Absolute Maximum Ratings Ambiant Temperature Under Bias ......................- Storage Temperature .................................... - 150 C Voltage ......................................-0 6. Voltage on Any Pin to ...
Page 187
Symbol Parameter R Internal reset pull-up resistor RST Power down consumption Power Supply current in IDLE mode CCIDLE Power Supply current in Active mode I (AT89C5122) with DC/DC ON CCOP Power Supply current in Active mode I ...
Page 188
I Current Test Conditions CC LED’s Symbol Parameter I Output Low Current, P3.0 and P3.7 LED modes OL Note - + AT8xC5122/23 188 Figure 111. Power Down Mode All other pins ...
Page 189
Smart Card Interface Card VCC 5V (for IEC7816-3 Class A cards) Symbol Parameter Vcc Power Supply CI Card Supply Current overflow CC_ovf CV Card Supply Voltage CC Ripple on Card Voltage CV Card Supply Voltage during spike on Icc CC ...
Page 190
Card VCC 1.8V Power Supply (for IEC7816-3 Class C cards) Symbol Parameter Vcc Power Supply CI Card Supply Current overflow CC_ovf CV Card Supply Voltage CC T CVcc to 0 OFF CVcc ON Notes: 1. Test conditions, ...
Page 191
Smart Card CIO, DC Parameters Symbol Parameter I Output Low Current OL V Output High Voltage OH I Output High Current OH Voltage Stability t t Rise and Fall delays R F Note: 1. The voltage on RST should remain ...
Page 192
USB Interface AT8xC5122/23 192 Figure 113. USB Interface Symbol Parameter V USB Reference Voltage REF V Input High Voltage for D+ and D- (driven Input High Voltage for D+ and D- (floating) IHZ V Input Low Voltage for ...
Page 193
AC Parameters Explanation of the AC Symbols External Program Memory Characteristics 4202E–SCR–06/06 Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of ...
Page 194
External Program Memory Read Cycle ALE PSEN INSTR IN PORT 0 ADDRESS PORT 2 OR SFR-P2 AT8xC5122/23 194 Table 115. AC Parameters for a Variable Clock Symbol Type T Min LHLL T Min AVLL T Min LLAX T Max LLIV ...
Page 195
External Data Memory Characteristics 4202E–SCR–06/06 Table 116. Symbol Description Symbol Parameter T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD RHDZ ...
Page 196
External Data Memory Write Cycle ALE PSEN WR PORT 0 PORT 2 AT8xC5122/23 196 Table 117. AC Parameters for a Variable Clock Symbol Type T Min RLRH T Min WLWH T Max RLDV T Min RHDX T Max RHDZ T ...
Page 197
External Data Memory Read Cycle ALE PSEN RD PORT 0 PORT 2 Serial Port Timing - Shift Register Mode 4202E–SCR–06/06 T LLWL T LLAX A0-A7 T AVWL ADDRESS OR SFR-P2 Table 118. Symbol Description ( MHz) Symbol T ...
Page 198
Shift Register Timing Waveform INSTRUCTION ALE CLOCK OUTPUT DATA WRITE to SBUF INPUT DATA External Clock Drive Characteristics (XTAL1) External Clock Drive Waveforms AC Testing Input/Output Waveforms AT8xC5122/23 198 XLXL T XHQX T QVXH 0 1 ...
Page 199
Float Waveforms Clock Waveforms INTERNAL CLOCK XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST PORT (P1. ...
Page 200
USB Interface V CRS Differential Data Lines AT8xC5122/23 200 This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent ...