AT85C5122D-SISUM Atmel, AT85C5122D-SISUM Datasheet - Page 21

• Manufacturer Part Number: AT85C5122D-SISUM
• Description: RFID Modules & Development Tools 3-5.5V Smart Card Reader
• Manufacturer: Atmel

Specifications of AT85C5122D-SISUM

• Product: RFID Readers

Data Memory
Managament
RAM Achitecture
XRAM Achitecture
4202E–SCR–06/06
All device versions implements :
- 256 Bytes of RAM to increase data parameter handling and high level language usage
- 512 bytes of XRAM (Extended RAM) to store program data.
The internal RAM is mapped into three separate segments :
•
•
•
The Upper 128 bytes and SFR’s have the same address space but are physically
separated.
When an instruction accesses an internal location above address 7Fh, the CPU knows
whether the access is in the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
•
•
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings. If M0 is set, the read and write pulses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
Depending on the state of EXTRAM bit in AUXR register (See Table 5 on page 24), the
MCU fetches data from internal or external XRAM.
If EXTRAM=0 (reset condition), the MCU fetches the data from internal XRAM. The size
of internal XRAM is configured by the bit XRS0 in AUXR register (See Table 5 on page
24).
The XRAM logically occupies the first bytes of external data memory. The bit XRS0 can
be used to hide a part of the available XRAM . This can be useful if external peripherals
are mapped at addresses already used by the internal XRAM.
The XRAM is indirectly addressed, using the MOVX instruction in combination with any
of the registers R0, R1 of the selected bank or DPTR.
For example, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at
address 0A0H rather than external memory.
The Lower 128 bytes (addresses 00h to 7Fh) are directly and indirectly
addressable.
The Upper 128 bytes (addresses 80h to FFh) are indirectly addressable only.
The Special Function Registers (SFRs) (addresses 80h to FFh) are directly
addressable only.
Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, accesses the SFR at location 0A0h (which is P2).
Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte
at address 0A0h, rather than P2 (whose address is 0A0h).
Table 4. XRAM Size Configuration
XRS0
0
1
(Reset condition)
XRAM size
256 Bytes
512 bytes
Start
000h
000h
Address
AT8xC5122/23
0FFh
1FFh
End
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