AD9980KSTZ-80 Analog Devices Inc, AD9980KSTZ-80 Datasheet - Page 22

• Manufacturer Part Number: AD9980KSTZ-80
• Description: IC,Data Acquisition Signal Conditioner,3-CHANNEL,8-BIT,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9980KSTZ-80

• Applications: Video
• Interface: Analog
• Voltage - Supply: 3.13 V ~ 3.47 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9980/PCBZ - KIT EVALUATION AD9980
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9980
TWO-WIRE SERIAL REGISTER MAP
The AD9980 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to
write and read the control registers through the two-wire serial interface port.
Table 12. Control Register Map
Hexadecimal
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
Read and
Write or
Read Only
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits
7:0
7:0
7:4
7:6
5:3
2
7:3
6:0
7:0
6:0
7:0
6:0
7:0
7:0
7
7:0
7
7:0
7
7:0
Default
Value
0110 1001
1101 ****
01** ****
**00 1***
**** *0**
1000 0***
*100 0000
0000 0000
*100 0000
0000 0000
*100 0000
0000 0000
0100 0000
0*** ****
0100 0000
0*** ****
0100 0000
0*** ****
0010 0000
Chip Revision
Phase Adjust
Register
Name
PLL Div MSB
PLL Div LSB
VCO/CPMP
Red Gain MSB
Green Gain
MSB
Blue Gain MSB
Red Offset MSB
Red Offset
Green Offset
MSB
Green Offset
Blue Offset
MSB
Blue Offset
Sync Separator
Threshold
Rev. 0 | Page 22 of 44
Description
An 8-bit register that represents the silicon revision level.
This register is for Bits [11:4] of the PLL divider. Larger values mean
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. (This will give the PLL more time to
lock).
Bits [7:4] LSBs of the PLL divider word. Links to the PLL Div MSB to
make a 12-bit register.
Bits [7:6] VCO Range. Selects VCO frequency range.
(See PLL description).
Bits [5:3] Charge Pump Current. Varies the current that drives the
low-pass filter. (See PLL description).
Bit 2. External Clock Enable
ADC clock phase adjustment. Larger values mean more delay.
(1 LSB = T/32).
7-Bit Red Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.
Must be written to 0x00 following a write of Register 0x05 for
proper operation.
7-Bit Green Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.
Must be written to 0x00 following a write of Register 0x07 for
proper operation.
7-Bit Blue Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.
Must be written to 0x00 following a write of Register 0x09 for
proper operation.
8-Bit MSB of the Red Channel Offset Control. Controls the dc offset
(brightness) of each respective channel. Bigger values decrease
brightness.
Linked with 0x0B to form the 9-bit red offset that controls the dc
offset (brightness) of the red channel in auto-offset mode.
8-Bit MSB of the Green Channel Offset Control. Controls the dc
offset (brightness) of each respective channel. Bigger values
decrease brightness.
Linked with 0x0D to form the 9-bit green offset that controls the
dc offset (brightness) of the green channel in auto-offset mode.
8-Bit MSB of the Red Channel Offset Control. Controls the dc offset
(brightness) of each respective channel. Bigger values decrease
brightness.
Linked with 0x0F to form the 9-bit blue offset that controls the dc
offset (brightness) of the blue channel in auto-offset mode.
This register sets the threshold of the sync separator’s digital
comparator.
1
2
2
2
1
1
1
1
Preliminary Technical Data