AD9980KSTZ-80 Analog Devices Inc, AD9980KSTZ-80 Datasheet - Page 24

• Manufacturer Part Number: AD9980KSTZ-80
• Description: IC,Data Acquisition Signal Conditioner,3-CHANNEL,8-BIT,CMOS,QFP,80PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9980KSTZ-80

• Applications: Video
• Interface: Analog
• Voltage - Supply: 3.13 V ~ 3.47 V
• Package / Case: 80-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9980/PCBZ - KIT EVALUATION AD9980
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9980
Hexadecimal
Address
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
Read and
Write or
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
Bits
5
4
3
2
1
0
7:0
7:0
7
6
5
4:3
2:0
7:0
7:3
2
1:0
7
6
Default
Value
**1* ****
***0 ****
**** 0***
**** *0**
**** **0*
**** ***0
0000 1000
0010 0000
0*** ****
*1** ****
**0* ****
***1 1***
**** *011
1111 1111
0111 1***
**** *0**
**** **00
*** ****
*0** ****
TestReg0
SOG Control
Register
Name
Clamp
Placement
Clamp
Duration
Clamp and
Offset
Power
Rev. 0 | Page 24 of 44
Description
Coast Input Polarity.
This bit is used only if 0x18, Bit 6 is set to 1.
0 = Active low external Coast.
1 = Active high external Coast.
Clamp Source Select.
0 = Use the internal clamp generated from Hsync.
1 = Use the external clamp signal.
Red Clamp.
0 = Clamp the red channel to ground.
1 = Clamp the red channel to midscale.
Green Clamp.
0 = Clamp the green channel to ground.
1 = Clamp the green channel to midscale.
Blue Clamp.
0 = Clamp the blue channel to ground.
1 = Clamp the blue channel to midscale.
Must be set to 0 for proper operation.
Places the clamp signal an integer of clock periods after the trailing
edge of the Hsync signal.
Number of clock periods that the clamp signal is actively clamping.
External clamp polarity override.
0 = The chip selects the clamp polarity.
1 = The polarity of the clamp signal is set by 0x1B, Bit 6.
External Clamp Input Polarity. This bit is used only if 0x1B, Bit 7 is
set to 1.
0 = Active low external clamp.
1 = Active high external clamp.
0 = Auto-offset is disabled.
1 = Auto-offset is enabled (offsets become the desired clamp
code).
This selects how often the auto-offset circuit operates. 00 = every
clamp; 01 = 16 clamps; 10 = every 64 clamps; 11 = every Vsync.
Must be written to default (011) for proper operation.
Must be set to 0xFF for proper operation.
SOG slicer threshold. Sets the voltage level of the SOG slicer’s
comparator.
SOGOUT Polarity.
Sets the polarity of the signal on the SOGOUT pin.
0 = Active low SOGOUT.
1 = Active high SOGOUT.
SOGOUT Select.
00 = Raw SOG from sync slicer (SOG0 or SOG1).
01 = Raw Hsync (Hsync0 or Hsync1).
10 = Regenerated sync from sync filter.
11 = Filtered sync from sync filter.
Channel Select Override.
0 = The chip determines which input channels to use.
1 = The input channel selection is determined by 0x1E, Bit 6.
Channel Select.
Input channel select: this is used only if 0x1E, Bit 7 is set to 1, or if
syncs are present on both channels.
0 = Channel 0 syncs and data are selected.
1 = Channel 1 syncs and data are selected.
Preliminary Technical Data