ADUC7036CCPZ-RL Analog Devices Inc, ADUC7036CCPZ-RL Datasheet - Page 110

• Manufacturer Part Number: ADUC7036CCPZ-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036CCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-VFQFN Exposed Pad, CSP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7036
SERIAL PERIPHERAL INTERFACE
The ADuC7036 features a complete hardware serial peripheral
interface (SPI) on chip. SPI is an industry-standard synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and received simultaneously, that is, full duplex.
The SPI interface is operational only with core clock divider bits
(POWCON[2:0] = 0000 or 001).
The SPI port can be configured for master or slave operation
and consists of four pins that are multiplexed with four GPIOs.
The four SPI pins are MISO, MOSI, SCLK, and SS . The pins to
which these signals are connected are shown in
Table 87. SPI Output Pins
Pin
GP0 (GPIO Mode 1)
GP1 (GPIO Mode 1)
GP2 (GPIO Mode 1)
GP3 (GPIO Mode 1)
MISO PIN
The MISO (master input, slave output) pin is configured as an
input line in master mode and as an output line in slave mode.
The MISO line on the master (data in) should be connected to
the MISO line in the slave device (data out). The data is transferred
as byte-wide (8-bit) serial data, MSB first.
MOSI PIN
The MOSI (master output, slave input) pin is configured as an
output line in master mode and as an input line in slave mode.
The MOSI line on the master (data out) should be connected to
the MOSI line in the slave device (data in). The data is transferred
as byte-wide (8-bit) serial data, MSB first.
SCLK PIN
The SCLK (master serial clock) pin is used to synchronize the
data being transmitted and received through the MOSI SCLK
period. Therefore, a byte is transmitted/received after eight
SCLK periods. The SCLK pin is configured as an output in
master mode and as an input in slave mode.
SPI
Pin Function
SS
SCLK
MISO
MOSI
Description
Serial clock
Master input, slave output
Master output, slave input
Chip select
Table 87
.
Rev. C | Page 110 of 132
In master mode, polarity and phase of the clock is controlled by
the SPICON register, and the bit rate is defined in the SPIDIV
register using the SPI baud rate calculation, as follows:
The maximum speed of the SPI clock is dependent on the clock
divider bits and is summarized in Table 88.
Table 88. SPI Speed vs. Clock Divider Bits in Master Mode
Setting of CD Bits
0
1
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data of up to 5.12 Mb from an external master when
CD = 0. The formula to determine the maximum speed is as
follows:
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important to use the same polarity and phase configurations for
the master and slave devices.
SS PIN
In SPI slave mode, a transfer is initiated by the assertion of SS ,
an active low input signal. The SPI port transmits and receives
eight bits of data, and then the transfer is concluded by the
deassertion of SS . In slave mode, SS is always an input.
SPI REGISTER DEFINITIONS
The following MMR registers are used to control the SPI
interface:
•
•
•
•
•
SPICON: 16-bit control register
SPISTA: 8-bit, read only status register
SPIDIV: 8-bit, serial clock divider register
SPITX: 8-bit, write only transmit register
SPIRX: 8-bit, read only receive register
f
f
SERIAL
SERIAL
CLOCK
CLOCK
=
2
=
×
20
SPIDIV
0x05
0x0B
f
1 (
HCLK
.
4
48
+
SPIDIV
MHz
)
Maximum SCLK (MHz)
1.667
0.833
(3)
(4)