ADUC7036CCPZ-RL Analog Devices Inc, ADUC7036CCPZ-RL Datasheet - Page 116

• Manufacturer Part Number: ADUC7036CCPZ-RL
• Description: Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036CCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-VFQFN Exposed Pad, CSP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7036
LIN (LOCAL INTERCONNECT NETWORK) INTERFACE
The ADuC7036 features high voltage physical interfaces between
the ARM7 MCU core and an external LIN bus. The LIN inter-
face operates as a slave only interface, operating from 1 kBaud
to 20 kBaud, and it is compatible with the LIN 2.0 standard.
The pull-up resistor required for a slave node is on chip,
reducing the need for external circuitry. The LIN protocol is
emulated using the on-chip UART, an IRQ, a dedicated LIN
timer, and the high voltage transceiver (also incorporated on
chip) as shown in Figure 46. The LIN is clocked from the low
power oscillator for the break timer, and a 5 MHz output from
the PLL is used for the synchronous byte timing.
GPSDAT[21]
GP2DAT[29]
GPIO_12
131kHz
LHS INTERRUPT
5MHz
AND
IRQEN[7]
HARDWARE
LHSVAL0
LHSVAL1
UART
LHS
RxD ENABLE
LHSCON0[8]
GP2CON[20]
FUNCTION
RxD
TxD
GPIO_12
SELECT
INTERRUPT
LOGIC
LHS
Figure 46. LIN I/O Block Diagram
DISABLE
OUTPUT
SHORT-CIRCUIT
HVCFG0[1:0]
LIN MODE
HVCFG1[2]
CONTROL
FOUR LIN
INTERRUPT
SOURCES:
BREAK LHSSTA[0]
START LHSSTA[1]
STOP LHSSTA[2]
BREAK
ERROR LHSSTA[4]
Rev. C | Page 116 of 132
INPUT
VOLTAGE
THRESHOLD
REFERENCE
BPF
TRIP REFERENCE
SHORT-CIRCUIT
INTERNAL
LIN MMR DESCRIPTION
The LIN hardware synchronization (LHS) functionality is con-
trolled through five MMRs. The function of each MMR is as
follows:
•
•
•
•
•
LHSSTA: LHS status register. This MMR contains infor-
mation flags that describe the current status on the
interface.
LHSCON0: LHS Control Register 0. This MMR controls
the configuration of the LHS timer.
LHSCON1: LHS start and stop edge control register. This
MMR dictates on which edge of the LIN synchronization
byte the LHS starts/stops counting.
LHSVAL0: LHS synchronization 16-bit timer. This MMR is
controlled by LHSCON0.
LHSVAL1: LHS break timer register.
VDD
INTERNAL
SHORT-CIRCUIT
SENSE
RESISTOR
OVERVOLTAGE
PROTECTION
LIN ENABLE
(INTERNAL
HVCFG0[5]
PULL-UP)
EXTERNAL
LIN PIN
IO_VSS
SCR
VDD
MASTER ECU
PROTECTION
DIODE
MASTER ECU
PULL-UP
C
LOAD