ADUC7036CCPZ-RL Analog Devices Inc, ADUC7036CCPZ-RL Datasheet - Page 94
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ADUC7036CCPZ-RL
Manufacturer Part Number
ADUC7036CCPZ-RL
Description
Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7036QSPZ.pdf
(132 pages)
Specifications of ADUC7036CCPZ-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
48-VFQFN Exposed Pad, CSP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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ADuC7036
GPIO Port1 Clear Register
Name: GP1CLR
Address: 0xFFFF0D38
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish
this using the GP1CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP1DAT).
Table 69. GP1CLR MMR Bit Designations
Bit
31 to 18
17
16
15 to 0
GPIO Port2 Clear Register
Name: GP2CLR
Address: 0xFFFF0D48
Access: Write only
Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish
this using the GP2CLR MMR without having to modify or maintain the status of the GPIO pins (as user code requires when using GP2DAT).
Table 70. GP2CLR MMR Bit Designations
Bit
31 to 23
22
21
20 to 18
17
16
15 to 0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Port 1.1 clear bit.
Set to 1 by user code to clear the external GPIO_6 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_6 pin.
Port 1.0 clear bit.
Set to 1 by user code to clear the external GPIO_5 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_5 pin.
Reserved. These bits are reserved and should be written as 0 by user code.
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Port 2.6 clear bit.
Set to 1 by user code to clear the external GPIO_13 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin.
Port 2.5 clear bit.
Set to 1 by user code to clear the external GPIO_12 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin.
Reserved. These bits are reserved and should be written as 0 by user code.
Port 2.1 clear bit.
Set to 1 by user code to clear the external GPIO_8 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_8 pin.
Port 2.0 clear bit.
Set to 1 by user code to clear the external GPIO_7 pin low.
Clearing this bit to 0 via user software has no effect on the external GPIO_7 pin.
Reserved. These bits are reserved and should be written as 0 by user code.
Rev. C | Page 94 of 132
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