ADUC7060BSTZ32 Analog Devices Inc, ADUC7060BSTZ32 Datasheet - Page 52

• Manufacturer Part Number: ADUC7060BSTZ32
• Description: DUAL 24-BIT AFE AND ARM 7 I.C
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7060BSTZ32

• Design Resources: 4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) Low power, Long Range, ISM Wireless Measuring Node (CN0164)
• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 2.625 V
• Data Converters: A/D 5x24b, 8x24b, D/A 1x14b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Cpu Family: ADuC7xxx
• Device Core: ARM7TDMI
• Device Core Size: 16/32Bit
• Frequency (max): 10.24MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 4KB
• # I/os (max): 14
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.625V
• Operating Supply Voltage (min): 2.375V
• On-chip Adc: 2(4-chx24-bit)
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: ADuC7xxx
• Maximum Speed: 10.24 MHz
• Operating Supply Voltage: 2.5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 14
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

ADuC7060/ADuC7061
Primary Channel ADC Comparator Threshold Register
Name:
Address:
Default value:
Access:
Function:
ADC0ATH
0xFFFF054C
0x00000000
Read and write
This 32-bit MMR holds the threshold value for
the accumulator comparator of the primary
channel. When the accumulator value in
ADC0ACC exceeds the value in ADC0ATH,
the ADC0ATHEX bit in ADCSTA is set. This
causes an interrupt if the corresponding bit in
ADCMSKI is also enabled.
CLEAR
ADC0
ADC1
(DEFAULT = 1)
COUNTER
ADC0RCR
ADC0RCV
f
PRIMARY
ADC
Figure 17. Primary ADC Accumulator/Comparator/Counter Block Diagram
ADC
f
ADC
(READABLE)
16
OVERRANGE
≥
FAST
ADC0TH
INTERRUPT
(ADC0RDY)
|ABSVAL|
f
Rev. B | Page 52 of 108
ADC
INTERRUPT
(ADC0OVR)
ACCUMULATOR
≥
ADC0ACC
f
ADC
Table 61. ADC0ATH MMR Bit Designations
Bit
31:0
ADC0ATH
OPTION: UP/RESET
32
UP/DOWN
ADC0THV
ADC0THC
Description
ADC0 32-bit comparator threshold register of the
accumulator.
(READABLE)
≥
≥
INTERRUPT
(ADC0ATHEX)
INTERRUPT
(ADC0THEX)