ADV7393BCPZ-REEL Analog Devices Inc, ADV7393BCPZ-REEL Datasheet - Page 46

• Manufacturer Part Number: ADV7393BCPZ-REEL
• Description: IC,TV/VIDEO CIRCUIT,Video Encoder,LLCC,40PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7393BCPZ-REEL

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Applications: Set-Top Boxes, Video Players, Displays
• Voltage - Supply, Analog: 2.6 V ~ 3.46 V
• Voltage - Supply, Digital: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADV7393-DBRDZ - BOARD EVAL FOR ADV7393EVAL-ADV7393EBZ - BOARD EVAL FOR ADV7393 ENCODER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7390/ADV7391/ADV7392/ADV7393
ADV7392/ADV7393 INPUT CONFIGURATION
The ADV7392/ADV7393 support a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7392/ADV7393 default to standard definition
(SD) mode on power-up. Table 36 provides an overview of all
possible input configurations. Each input mode is described in
detail in this section.
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
Standard definition YCrCb data can be input in 4:2:2 format over
an 8-, 10-, or 16-bit bus. SD RGB data can be input in 4:4:4 format
over a 16-bit bus.
A 27 MHz clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported in 8-bit and 10-bit modes.
8-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0;
Subaddress 0x88, Bits[4:3] = 00
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P8, with Pin P8 being the LSB. The
ITU-R BT.601/656 input standard is supported.
10-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0;
Subaddress 0x88, Bits[4:3] = 10
In 10-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P6, with Pin P6 being the LSB. The ITU-
R BT.601/656 input standard is supported.
Table 36. ADV7392/ADV7393 Input Configuration
Input Mode
000
001
010
111
1
2
3
4
The input mode is determined by Subaddress 0x01, Bits[6:4].
In SD mode, the width of the input data is determined by Subaddress 0x88, Bits[4:3].
External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.
ED = enhanced definition = 525p and 625p.
8-bit
10-bit
SD
8-bit
10-bit
16-bit
16-bit
ED/HD-SDR (16-bit)
ED/HD-DDR
8-bit
10-bit
ED (at 54 MHz)
2
1
3
3
4
P15
P14
P13
B
P12
YCrCb
YCrCb
YCrCb
Y
Y
Rev. B | Page 46 of 108
P11
YCrCb
YCrCb
YCrCb
SD RGB input enable (0x87[7]) = 0
SD RGB input enable (0x87[7]) = 1
ED/HD input format (0x33[2]) = 0
ED/HD input format (0x33[2]) = 1
ED/HD input format (0x33[2]) = 0
ED/HD input format (0x33[2]) = 1
P10
16-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0;
Subaddress 0x88, Bits[4:3] = 01
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with Pin P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 5).
16-Bit 4:4:4 RGB Mode
Subaddress 0x87, Bit 7 = 1
In 16-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin P4 to Pin P0, the green pixel data is input on Pin P10 to
Pin P5, and the blue pixel data is input on Pin P15 to Pin P11.
The P0, P5, and P11 pins are the respective bus LSBs.
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 6).
P9
P8
DECODER
MPEG2
G
P7
Figure 56. SD Example Application
YCrCb
P6
27MHz
8/10
2
P5
CLKIN
P[15:8]/P[15:6]
HSYNC
P4
VSYNC,
ADV7392/
ADV7393
CrCb
CrCb
P3
P2
R
P1
P0