ADV7393BCPZ-REEL Analog Devices Inc, ADV7393BCPZ-REEL Datasheet - Page 96

• Manufacturer Part Number: ADV7393BCPZ-REEL
• Description: IC,TV/VIDEO CIRCUIT,Video Encoder,LLCC,40PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7393BCPZ-REEL

• Design Resources: Reconstruction Video Filter Using ADA4430-1 Amplifier After ADV7393 Video Encoder (CN0101)
• Applications: Set-Top Boxes, Video Players, Displays
• Voltage - Supply, Analog: 2.6 V ~ 3.46 V
• Voltage - Supply, Digital: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADV7393-DBRDZ - BOARD EVAL FOR ADV7393EVAL-ADV7393EBZ - BOARD EVAL FOR ADV7393 ENCODER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7390/ADV7391/ADV7392/ADV7393
Table 84. 8-Bit 625i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x8A
Table 85. 8-Bit 625i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
Table 86. 8-Bit 625i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x8A
Table 87. 10-Bit 625i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
Setting
0x02
0x1C
0x00
0x11
0xC1
0x0C
Setting
0x02
0x1C
0x00
0x10
0x11
0xC1
Setting
0x02
0x1C
0x00
0x10
0x11
0xC1
0x0C
Setting
0x02
0x1C
0x00
0x11
0xC1
0x10
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled.
10-bit input enabled.
Rev. B | Page 96 of 108
Table 88. 10-Bit 625i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
0x8A
Table 89. 10-Bit 625i YCrCb In, CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
0x8A
0x8C
0x8D
0x8E
0x8F
Table 90. 10-Bit 625i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x88
0x02
0x1C
0x00
0x11
0xC1
0x10
0x0C
0x02
0x1C
0x00
0x11
0xC3
0x10
0x0C
0xCB
0x8A
0x09
0x2A
0x02
0x1C
0x00
0x10
0x11
0xC1
0x10
Setting
Setting
Setting
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel Data Valid. CVBS/Y-C (S-Video)
Out. SSAF PrPb filter enabled. Active
video edge control enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL mode (27 MHz input clock).
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled.
10-bit input enabled.