AM29LV256MH113REI AMD (ADVANCED MICRO DEVICES), AM29LV256MH113REI Datasheet - Page 47

• Manufacturer Part Number: AM29LV256MH113REI
• Description: Flash Memory IC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV256MH113REI

• Memory Size: 256Mbit
• Package/case: 56-TSOP
• Access Time, Tacc: 110nS
• Mounting Type: Surface Mount
• Supply Voltage: 3V

other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or
write-to-buffer time has exceeded a specified internal
pulse count limit. Under these conditions DQ5 produces a
“1,” indicating that the program or erase cycle was not suc-
cessfully completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
In all these cases, the system must write the reset
command to return the device to the reading the array
(or to erase-suspend-read if the device was previously
in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.
December 16, 2005
Standard
Suspend
Suspend
Program
Write-to-
maximum timing limits. Refer to the section on DQ5 for more information.
Erase
Buffer
Mode
Mode
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Erase-Suspend-Program
(Embedded Program)
Busy (Note 3)
Abort (Note 4)
Program-
Suspend
Suspend
Erase-
Read
Read
Status
Program-Suspended
Sector
Non-Program
Suspended Sector
Erase-Suspended
Sector
Non-Erase Suspended
Sector
Table 13. Write Operation Status
Figure
D A T A S H E E T
(Note 2)
DQ7#
DQ7#
DQ7#
DQ7#
DQ7
8).
0
1
Am29LV256M
No toggle
Toggle
Toggle
Toggle
Toggle
Toggle
DQ6
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the
Sequence
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 13
status bits.
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation
was aborted. Under these conditions DQ1 produces a
“ 1 ” .
Write-to-Buffer-Abort-Reset command sequence to re-
turn the device to reading array data. See
Invalid (not allowed)
T h e
(Note 1)
shows the status of DQ3 relative to the other
DQ5
section.
0
0
0
0
0
0
Data
Data
s y s t e m
DQ3
N/A
N/A
N/A
N/A
N/A
1
No toggle
(Note 2)
Toggle
Toggle
Sector Erase Command
DQ2
m u s t
N/A
N/A
N/A
i s s u e
DQ1
N/A
N/A
N/A
0
0
1
Write Buffer
RY/BY#
0
0
1
1
1
1
0
0
0
t h e
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